SMI Status Register 1 (SMI_STS1)
Register Location: <PM1_BLK>+12h System I/O Space
Default Value:00h on Vbat POR
Attribute:Read/Write
Size:8-bits
NAME
DESCRIPTION
SMI Status Register 1
This register is used to read the status of the SMI inputs.
Default = 0x00
on Vbat POR
The following bits must be cleared at their source.
Bit[0] Reserved
Bit[1] PINT (Parallel Port Interrupt)
Bit[2] U2INT (UART 2 Interrupt)
Bit[3] U1INT (UART 1 Interrupt)
Bit[4] FINT (Floppy Disk Controller Interrupt)
Bit[5] GPINT2 (Group Interrupt 2)
Bit[6] GPINT1 (Group Interrupt 1)
Bit[7] WDT (Watch Dog Timer)
SMI Status Register 2 (SMI_STS2)
Register Location: <PM1_BLK>+13h System I/O Space
Default Value:00h on Vbat POR
Attribute:Read/Write
Size:8-bits
NAME
DESCRIPTION
SMI Status Register
2
This register is used to read the status of the SMI inputs.
Bit[0] MINT: Mouse Interrupt. Cleared at source.
Bit[1] KINT: Keyboard Interrupt. Cleared at source.
Default = 0x00
on Vbat POR
Bit[2] IRINT: This bit is set by a transition on the IR pin (RXD2 or IRRX2 as
selected by Bit 6 of Configuration Register 0xF1 in Logical Device 5, i.e.,
after the MUX). Cleared by a read of this register.
Bit[3] BINT: Cleared by a read of this register.
Bit[4] P12: 8042 P1.2. Cleared at source
Bits[5:6] Reserved
Bit[7] SLP_EN_SMI. The SLP_EN SMI status bit. Cleared by a read of this
register. (See Sleep Enable Config Reg.)
0=no SMI due to setting SLP_EN bit
1=SMI generated due to setting SLP_EN bit.
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SMSC [ SMSC CORPORATION ]
