OBF(Output Buffer Full) - This flag is set to
whenever the FDC37B78x CPU write to the output
data register (DBB). When the host system reads
the output data register, this bit is automatically
reset.
Status Register
This register is cleared on a reset. This register is
read-only for the Host and read/write by the
FDC37B78x CPU.
UDWritable by FDC37B78x CPU. These bits are
user-definable.
EXTERNAL CLOCK SIGNAL
The FDC37B78x Keyboard Controller clock source
is a 12 MHz clock generated from a 14.318 MHz
clock. The reset pulse must last for at least 24 16
MHz clock periods. The pulse-width requirement
applies to both internally (Vcc POR) and externally
generated reset signals. In powerdown mode, the
external clock signal is not loaded by the chip.
C/D(Command Data)-This bit specifies whether
the input data register contains data or
a
command (0 = data, 1 = command). During a host
data/command write operation, this bit is set to "1"
if SA2 = 1 or reset to "0" if SA2 = 0.
IBF(Input Buffer Full)- This flag is set to 1
whenever the host system writes data into the
input data register. Setting this flag activates the
FDC37B78x CPU's nIBF (MIRQ) interrupt if
enabled. When the FDC37B78x CPU reads the
input data register (DBB), this bit is automatically
reset and the interrupt is cleared. There is no
output pin associated with this internal signal.
DEFAULT RESET CONDITIONS
The FDC37B78x has one source of reset: an
external reset via the RESET_DRV pin. Refer to
TABLE 60 for the effect of each type of reset on
the internal registers.
TABLE 60 - RESETS
DESCRIPTION
KCLK
KDAT
MCLK
MDAT
HARDWARE RESET (RESET)
Input
Input
Input
Input
N/A
Host I/F Data Reg
Host I/F Status Reg
00H
N/A: Not Applicable
133
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