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FDC37B78X_07 参数 Datasheet PDF下载

FDC37B78X_07图片预览
型号: FDC37B78X_07
PDF下载: 下载PDF文件 查看货源
内容描述: 超级I / O控制器,支持ACPI ,实时时钟和消费性红外端口 [Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR]
分类和应用: 控制器时钟
文件页数/大小: 249 页 / 865 K
品牌: SMSC [ SMSC CORPORATION ]
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GATEA20 AND KEYBOARD RESET  
PORT 92 FAST GATEA20 AND KEYBOARD  
RESET  
The FDC37B78x provides two options for  
GateA20 and Keyboard Reset: 8042 Software  
Generated GateA20 and KRESET and Port 92  
Fast GateA20 and KRESET.  
Port 92 Register  
This port can only be read or written if Port 92  
has been enabled via bit 2 of the KRST_GA20  
Register (Logical Device 7, 0xF0) set to 1.  
This register is used to support the alternate  
reset (nALT_RST) and alternate A20 (ALT_A20)  
functions.  
Name  
Port 92  
92h  
24h  
Read/Write  
8 bits  
Location  
Default Value  
Attribute  
Size  
Port 92 Register  
Bit  
7:6  
5
4
3
Function  
Reserved. Returns 00 when read  
Reserved. Returns a 1 when read  
Reserved. Returns a 0 when read  
Reserved. Returns a 0 when read  
Reserved. Returns a 1 when read  
2
1
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be  
driven low. Writing a 1 to this bit causes the ALT_A20 signal to be driven high.  
Alternate System Reset. This read/write bit provides an alternate system reset  
function. This function provides an alternate means to reset the system CPU to  
effect a mode switch from Protected Virtual Address Mode to the Real Address  
Mode. This provides a faster means of reset than is provided by the Keyboard  
controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause  
the nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of  
500 ns. Before another nALT_RST pulse can be generated, this bit must be written  
back to a 0.  
0
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