The Configuration of the FDC37B72x is very
flexible and is based on the configuration
architecture implemented in typical Plug-and-Play
components. The FDC37B72x is designed for
motherboard applications in which the resources
required by their components are known. With its
flexible resource allocation architecture, the
FDC37B72x allows the BIOS to assign resources
at POST.
at POST. The INDEX and DATA ports are only
valid when the FDC37B72x is in Configuration
Mode.
The SYSOPT pin is latched on the falling edge of
the RESET_DRV or on Vcc Power On Reset to
determine the configuration register's base
address. The SYSOPT pin is used to select the
CONFIG PORT's I/O address at power-up. Once
powered up the configuration port base address
can be changed through configuration registers
CR26 and CR27. The SYSOPT pin is a
hardware configuration pin which is shared
with the nRTS1 signal on pin 115. During reset
this pin is a weak active low signal which sinks
30µA. Note: All I/O addresses are qualified with
AEN.
SYSTEM ELEMENTS
Primary Configuration Address Decoder
After a hard reset (RESET_DRV pin asserted) or
Vcc Power On Reset the FDC37B72x is in the
Run Mode with all logical devices disabled. The
logical devices may be configured through two
standard Configuration I/O Ports (INDEX and
The INDEX and DATA ports are effective only
when the chip is in the Configuration State.
DATA)
by
placing
the FDC37B72x into
Configuration Mode.
The BIOS uses these
configuration ports to initialize the logical devices
SYSOPT= 0
(Pull-down resistor)
Refer to Note 1
SYSOPT= 1
(10K Pull-up resistor)
PORT NAME
TYPE
Write
CONFIG PORT (Note 2)
INDEX PORT (Note 2)
DATA PORT
0x03F0
0x0370
0x0370
0x03F0
Read/Write
Read/Write
INDEX PORT + 1
Note 1: If using TTL RS232 drivers use 1K pull-down. If using CMOS RS232 drivers use 10K pull-down.
Note 2: The configuration port base address can be relocated through CR26 and CR27.
Entering the Configuration State
Exiting the Configuration State
The device enters the Configuration State when
the following Config Key is successfully written to
the CONFIG PORT.
The device exits the Configuration State when the
following Config Key is successfully written to the
CONFIG PORT.
Config Key = < 0x55>
Config Key = < 0xAA>
When in configuration mode, all logical devices
function properly.
Entering and exiting
configuration mode has no effect on the devices.
To program the configuration registers, the
following sequence must be followed:
1. Enter Configuration Mode
CONFIGURATION SEQUENCE
10
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