Fan Control Device with High Frequency PWM Support and Hardware Monitoring Features
Datasheet
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TACH1, TACH2, TACH3, TACH4
PWM2, PWM3
Since the test mode is XOR tree, the order of the signals in the tree is not important. SDA and SCL
are not included in the test tree.
8.2.22
Register 79h: SMSC Test Register
Table 8.39 Register 79h: SMSC Test Register
Register
Address
Read/
Write
Bit 7
Bit 0
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSb)
(LSb)
79h
R/W
SMSC Test Register
TST7
TST6
TST5
TST4 TST3 TST2
TST1
TST0
00h
This is a read/write register. Writing this register may produce unwanted results.
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
8.2.23
Register 7Ah: SMSC Test Register
Table 8.40 Register 7Ah: SMSC Test Register
Register
Address
Read/
Write
Bit 7
Bit 0
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSb)
(LSb)
7Ah
R
SMSC Test Register
RES
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
This is a read/write register. Writing this register may produce unwanted results.
8.2.24
Register 7Bh: SMSC Test Register
Table 8.41 Register 7Bh: SMSC Test Register
Register
Address
Read/
Write
Bit 7
Bit 0
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSb)
(LSb)
7Bh
R/W
SMSC Test Register
TST7
TST6
TST5
TST4
TST3
TST2
TST1
TST0
00h
This is a read/write register. Writing this register may produce unwanted results.
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
8.2.25
Register 7Ch: Special Function Register
Table 8.42 Register 7Ch: Special Function Register
Register
Address
Read/
Write
Bit 7
Bit 0
Default
Value
Register Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(MSb)
(LSb)
7Ch
R/W
Special Function
AVG2
AVG1
AVG0
SMSC
SMSC
INTEN
MONMD
LPMD
40h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
SMSC EMC6D103
Revision 0.4 (04-04-05)
DATA7S3HEET