Environmental Monitoring and Control Device
Datasheet
Bit[0]
1.5V Event Enable (EMC6D100 only)
Bit[1]
1.8V Event Enable (EMC6D100 only)
Bit[2]
2.5V Event Enable
Bit[3]
Vccp Event Enable
Bit[4]
3.3V Event Enable (EMC6D100 only)
Bit[5]
5V Event Enable
Bit[6]
12V Event Enable
Bit[7]
VCC Event Enable
These bits are defined as follows:
0=disable
1=enable.
See the figure in the “Interrupt Status Registers” section.
8.31 Register 7Fh: Configuration Register
BIT 7
BIT 0
(LSB)
RES
REGISTER READ/ REGISTER
DEFAULT
VALUE
BIT 6 BIT 5
BIT 4
BIT 3 BIT 2 BIT 1
ADDRESS WRITE
7Fh R/W
NAME
(MSB)
Configuration
INIT FTTST RES SUREN TRDY RES INT
10h
These registers become read only when the Lock bit is set. Any further attempts to write to these registers
shall have no effect.
This register contains the following bits:
Bit[1]
INT# pin enable: 0=INT# disabled, 1=INT# enabled (EMC6D100 only)
SMSC EMC6D100/EMC6D101
Page 63
Rev. 09-09-04
DATASHEET
SMSC [ SMSC CORPORATION ]
