Environmental Monitoring and Control Device
Datasheet
Table 8.15 - Hysteresis Settings
SETTING HYSTERESIS
0°C
0h
5h
Fh
5°C
15°C
8.25 Register 6F: XOR Test Register
BIT 7
(MSB)
BIT 0
(LSB)
REGISTER
ADDRESS
READ/
WRITE
REGISTER
NAME
DEFAULT
VALUE
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
XOR Test
Register
6Fh
R/W
RES
RES
RES
RES
RES
RES
RES
XEN
00h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall
have no effect.
The part incorporates an XOR tree test mode. When the test mode is enabled by setting the ‘XEN’ bit high
via SMBus, the part enters XOR test mode.
The following signals are included in the XOR test tree:
VID0, VID1, VID2, VID3, VID4
TACH1, TACH2, TACH3, TACH4
PWM2, PWM3, INT#
Since the test mode is XOR tree, the order of the signals in the tree is not important. SDA and SCL are not
included in the test tree.
8.26 Register 79h: Test Mode Register
BIT 7
(MSB)
BIT 0
(LSB)
REGISTER READ/ REGISTER
ADDRESS WRITE NAME
DEFAULT
VALUE
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
79h
R/W Test Mode ANTST2 ANTST1 ANTST0 OSCSEL ADCAVG EXTCLK DIGTST ADCTST
00h
This register becomes read only when the Lock bit is set. Any further attempts to write to this register shall
have no effect.
This register contains the following bits:
Bit[0]
Selects the ADC test mode. The default for this bit is zero, which deactivates ADC test mode.
Bit[1]
Selects the digital test mode. The default for this bit is zero, which deactivates digital test mode.
SMSC EMC6D100/EMC6D101
Page 59
Rev. 09-09-04
DATASHEET
SMSC [ SMSC CORPORATION ]
