Environmental Monitoring and Control Device
Datasheet
Bit[4]
FAN4 Event Enable
Bit[5]
Temp Interrupt Enable
Bit[6]
Ambient Event Enable
Bit[7]
Reserved
These bits are defined as follows:
0=disable
1=enable.
See the figure in the “Interrupt Status Registers” section.
8.33 Register 81h: TACH_PWM Register
BIT 7
(MSB)
BIT 0
(LSB)
REGISTER
ADDRESS
READ/
WRITE
REGISTER
NAME
DEFAULT
VALUE
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Fan
81h
R/W
Tach/PWM
Interrupt Select
T4H
T4L
T3H
T3L
T2H
T2L
T1H
T1L
A4h
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
This register is used to associate a PWM with a tachometer input. This association is used by the fan logic
to determine when to prevent a bit from being set in the interrupt status registers.
The fan tachometer will not cause a bit to be set in the interrupt status register:
a) if the current value in Current PWM Duty registers is 00h or
b) if the fan is disabled via the Fan Configuration Register.
Note: A bit will never be set in the interrupt status for a fan if its tachometer minimum is set to FFFFh.
See bit definition below.
Bits[1:0] Tach1. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[3:2] Tach2. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[5:4] Tach3. These bits determine the PWM associated with this Tach. See bit combinations below.
Bits[7:6] Tach4. These bits determine the PWM associated with this Tach. See bit combinations below.
SMSC EMC6D100/EMC6D101
Page 65
Rev. 09-09-04
DATASHEET
SMSC [ SMSC CORPORATION ]
