Environmental Monitoring and Control Device
Datasheet
Bit[2]
Selects the external clock test mode. The default for this bit is zero, which deactivates external oscillator
clock test mode.
Bit[3]
Selects either 8 or 1 averaging for the ADC test mode. The default for this bit is zero, which sets the
averaging to 8 for the ADC test mode. A one in this bit selects no averaging.
Bit[4]
Selects the oscillator clock to be muxed out on the VID2 pin. The default for this bit is zero, which
deactivates mux oscillator clock test mode.
Bits[7:5]
Are used by the analog block for test purposes. These three bits of register 4Ah are muxed out on pins
dig_test_an_pad[2:0]. These bits are also used to mux out either the SDATA line or the SCLK line to the
VID3 pin. If bits[7:5] are ‘001’, then the SDATA line is muxed out onto the VID3 pin. If bits[7:5] are ‘010’,
then the SCLK line is muxed out onto the VID3 pin.
8.27 Register 7Ah: Error Debug Register
BIT 7
(MSB)
BIT 0
(LSB)
REGISTER READ/ REGISTER
ADDRESS WRITE NAME
DEFAULT
VALUE
BIT 6 BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
7Ah
R
Error Debug RES ARA STOP INVADD RCV ROWR INVRW NONAC
00h
This register contains the following bits:
Bit[0]
Indicates that no NACK was generated by the host during either a read byte protocol or a receive byte
protocol.
Bit[1]
Indicates a read or a write was attempted to an invalid register location.
Bit[2]
Indicates a write to a read only register was attempted
Bit[3
Indicates a receive byte protocol was attempted when the address pointer register pointed to the 00h
location. This is the default register location on power on reset. As noted in the “Bus Protocols” section of
the “Hardware Monitoring Interface” section, the Internal Address register should be set up with a valid
address location by either a send byte protocol or a write byte protocol after power-on-reset, before the
receive byte protocol.
Bit[4]
Indicates an invalid slave address was detected.
SMSC EMC6D100/EMC6D101
Page 60
Rev. 09-09-04
DATASHEET
SMSC [ SMSC CORPORATION ]
