Environmental Monitoring and Control Device
Datasheet
8.11 Register 41h: Interrupt Status Register 1
BIT 7
(MSB)
BIT 0
(LSB)
REGISTER
ADDRESS
READ/
WRITE
REGISTER
NAME
DEFAULT
VALUE
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Interrupt
Status 1
41h
R-C1
INT23 ZN3
ZN2
ZN1
5V
3.3V Vccp 2.5V
00h
Note 1: This register is cleared on a read if no events are active
The Interrupt Status Register 1 bits are automatically set by the EMC6D100/EMC6D101 whenever the
2.5V, Vccp, 3.3V, or 5V input voltages violate the limits set in the limit and parameter registers or when the
measured temperature violates the limits set in the limit and parameter registers for any of the three
thermal zones.
This register holds a set bit until the event is read by software. The contents of this register are cleared
(set to 0) automatically by the EMC6D100/EMC6D101 after it is read by software, if the voltage or
temperature no longer violates the limits set in the limit and parameter registers. Once set, the Interrupt
Status Register 1 bits remain set until a read event occurs, even if the voltage or temperature no longer
violate the limits set in the limit and parameter registers.
This register contains a bit that indicates that a bit is set in one of the other interrupt status registers. If bit 7
is set, then a status bit is set in either Interrupt Status Register 2 or 3 (or both). Therefore, S/W can poll
this register, and only if bit 7 is set do the other registers need to be read. This bit is cleared (set to 0)
automatically by the EMC6D100/EMC6D101 if there are no bits set in Interrupt Status Registers 2 and 3.
This register is read only – a write to this register has no effect.
BIT
0
NAME
2.5V_Error
R/W
R
DEFAULT
DESCRIPTION
The EMC6D100/EMC6D101 automatically sets this bit to 1 when
the 2.5V input voltage is less than or equal to the limit set in the
2.5V Low Limit register or greater than the limit set in the 2.5V
High Limit register.
0
1
Vccp_Error
R
R
R
R
0
0
0
0
The EMC6D100/EMC6D101 automatically sets this bit to 1 when
the Vccp input voltage is less than or equal to the limit set in the
Vccp Low Limit register or greater than the limit set in the Vccp
High Limit register.
The EMC6D100/EMC6D101 automatically sets this bit to 1 when
the 3.3V input voltage is less than or equal to the limit set in the
3.3V Low Limit register or greater than the limit set in the 3.3V
High Limit register.
The EMC6D100/EMC6D101 automatically sets this bit to 1 when
the 5V input voltage is less than or equal to the limit set in the 5V
Low Limit register or greater than the limit set in the 5V High
Limit register.
The EMC6D100/EMC6D101 automatically sets this bit to 1 when
the temperature input measured by the Remote1- and Remote1+
is less than or equal to the limit set in the Processor (Zone1) Low
Temp register or greater than the limit set in Processor (Zone1)
High Temp register.
2
3
4
3.3V_Error
5V_Error
Zone 1 Limit
Exceeded
5
6
Zone 2 Limit
Exceeded
R
R
0
0
The EMC6D100/EMC6D101 automatically sets this bit to 1 when
the temperature input measured by the internal temperature
sensor is less than or equal to the limit set in the Internal (Zone2)
Low Temp register or greater than the limit set in the Internal
(Zone2) High Temp register.
The EMC6D100/EMC6D101 automatically sets this bit to 1 when
the temperature input measured by the Remote2- and Remote2+
is less than or equal to the limit set in the Remote (Zone3) Low
Temp register or greater than the limit set in the Remote (Zone3)
High Temp register.
Zone 3 Limit
Exceeded
SMSC EMC6D100/EMC6D101
Page 46
Rev. 09-09-04
DATASHEET
SMSC [ SMSC CORPORATION ]
