RPM-Based Fan Controller with Multiple Temperature Zones & Hardware Thermal Shutdown
Datasheet
Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status
Register that has bits set will clear the register and the corresponding bit in the Interrupt Status
Register if the error condition has been removed. If the error condition is persistent, reading the Error
Status Registers will have no effect.
7.14.1
Tcrit Status Register
The Tcrit Status Register stores which software enabled temperature channel has caused the
SYS_SHDN pin to be asserted. Each of the temperature channels must be associated with the
SYS_SHDN pin before they can be set (see Section 7.10, "Critical Temperature Limit Registers"). Once
the SYS_SHDN pin is asserted, it will be released when the temperature drops below the threshold
level; however, the individual status bit will not be cleared until read.
Bit 7 - HWS - This bit is set if the hardware set temperature channel caused the SYS_SHDN pin to
be asserted.
7.15
Fan Status Register
Table 7.22 Fan Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Fan Status
Register
DRIVE_
FAIL
FAN_
SPIN
FAN_
STALL
27h
R-C
WATCH
-
-
-
-
00h
The Fan Status Register contains the status bits associated with each fan driver.
Bit 7 - WATCH - This bit is asserted ‘1’ if the Watchdog timer has expired (see Section 6.10, "Watchdog
Timer").
Bit 5 - DRIVE_FAIL - Indicates that the RPM-based Fan Speed Control Algorithm cannot drive the Fan
to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT pin.
‘0’ - The RPM-based Fan Speed Control Algorithm can drive Fan to the desired target setting.
‘1’ - The RPM-based Fan Speed Control Algorithm cannot drive Fan to the desired target setting
at maximum drive.
Bit 1- FAN_SPIN - This bit is asserted ‘1’ if the Spin up Routine for the Fan cannot detect a valid
tachometer reading within its maximum time window. This bit can be masked from asserting the ALERT
pin.
Bit 0 - FAN_STALL - This bit is asserted ‘1’ if the tachometer measurement on the Fan detects a stalled
fan. This bit can be masked from asserting the ALERT pin.
7.16
Interrupt Enable Register
Table 7.23 Interrupt Enable Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
PWM_
INT_
EN
EXT3_
INT_
EN
EXT2_
INT_
EN
EXT1_
INT_
EN
INT_
INT_
EN
Interrupt
Enable
28h
R/W
-
-
-
00h
The Interrupt Enable Register controls the masking for each temperature channel. When a channel is
masked, it will not cause the ALERT pin to be asserted when an error condition is detected.
Revision 1.2 (10-08-09)
SMSC EMC2113
DATA5S4HEET
SMSC [ SMSC CORPORATION ]
