Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown
Datasheet
6.14
Fan Status Register
Table 6.19 Fan Status Register
B6 B5 B4 B3
ADDR
R/W
REGISTER
B7
B2
B1
B0
DEFAULT
Fan Status
Register
DRIVE
_FAIL2
DRIVE
_FAIL1
FAN_
SPIN2
FAN_
STALL2
FAN_
SPIN1
FAN_
STALL1
27h
R-C
WATCH
-
00h
The Fan Status Register contains the status bits associated with each fan driver. This register is
cleared when read if the error condition has been removed.
Bit 7 - WATCH - This bit is asserted ‘1’ if the host has not programmed the fan driver(s) within four (4)
seconds after power up.
Bit 6 - DRIVE_FAIL2 - Indicates that the RPM based Fan Speed Control Algorithm cannot drive Fan
2 to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT#
pin.
‘0’ - The RPM based Fan Speed Control Algorithm can drive Fan 2 to the desired target setting.
‘1’ - The RPM based Fan Speed Control Algorithm cannot drive Fan 2 to the desired target setting
at maximum drive.
Bit 6 - DRIVE_FAIL1 - Indicates that the RPM based Fan Speed Control Algorithm cannot drive Fan
1 to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT#
pin.
‘0’ - The RPM based Fan Speed Control Algorithm can drive Fan 1 to the desired target setting.
‘1’ - The RPM based Fan Speed Control Algorithm cannot drive Fan 1 to the desired target setting
at maximum drive.
Bit 3 - FAN_SPIN 2- This bit is asserted ‘1’ if the Spin up Routine for Fan 2 cannot detect a valid
tachometer reading within its maximum time window. This bit can be masked from asserting the
ALERT# pin.
Bit 2 - FAN_STALL 2 - This bit is asserted ‘1’ if the tachometer measurement on Fan 2 detects a stalled
fan. This bit can be masked from asserting the ALERT# pin.
Bit 1- FAN_SPIN1- This bit is asserted ‘1’ if the Spin up Routine for Fan 1 cannot detect a valid
tachometer reading within its maximum time window. This bit can be masked from asserting the
ALERT# pin.
Bit 0 - FAN_STALL1 - This bit is asserted ‘1’ if the tachometer measurement on Fan 1 detects a stalled
fan. This bit can be masked from asserting the ALERT# pin.
6.15
Interrupt Enable Register
Table 6.20 Interrupt Enable Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Interrupt
Enable
VOLT4_I
NT_EN
EXT4_I
NT_EN
EXT3_I
NT_EN
EXT2_I
NT_EN
EXT1_I
NT_EN
INT_IN
T_EN
28
R/W
-
-
00h
The Interrupt Enable Register controls the masking for each temperature channel. When a channel is
masked, it will not cause the ALERT# pin to be asserted when an error condition is detected.
Bit 5 - VOLT4_INT_EN - Allows the Voltage Input 4 channel to assert the ALERT# pin.
Revision 1.74 (05-08-08)
SMSC EMC2104
DATA6S0HEET
SMSC [ SMSC CORPORATION ]
