Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown
Datasheet
Bit 1- LOW - This bit is set to ‘1’ if any bit in the Low Status Register is set. This bit is automatically
cleared when the Low Status Register is read and the bits are cleared.
Bit 0 - FAULT - This bit is set to ‘1’ if any bit in the Diode Fault Register is set. This bit is automatically
cleared when the Diode Fault Register is read and the bits are cleared.
6.13
Error Status Registers
Table 6.18 Error Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
EXT4_
CRIT
EXT3_
CRIT
EXT2_
CRIT
EXT1
_CRIT
INT_
CRIT
1Fh
24h
25h
26h
R-C
Tcrit Status
HWS
-
-
00h
VOLT
4_HI
EXT4_
HI
EXT3_
HI
EXT2_
HI
EXT1
_HI
INT_
HI
R-C
R-C
R-C
High Status
Low Status
Diode Fault
-
-
-
-
-
-
00h
00h
00h
VOLT
4_LO
EXT4_
LO
EXT3_
LO
EXT2_
LO
EXT1
_LO
INT_L
O
EXT4_
FLT
EXT3_
FLT
EXT2_
FLT
EXT1
_FLT
-
-
The Error Status Registers report the specific error condition for all measurement channels with limits.
If any bit is set in the High, Low, or Diode Fault Status register, the corresponding High, Low, or Fault
bit is set in the Interrupt Status Register.
Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status
Register that has bits set will clear the register and the corresponding bit in the Interrupt Status
Register if the error condition has been removed. If the error condition is persistent, reading the Error
Status Registers will have no affect.
If any of the External Diode 1, External Diode 2, or External Diode 3 channels are configured as a
voltage input, then the corresponding temperature channel status bit will be set if the measured voltage
exceeds the high limit or falls below the low limit. In this condition, a diode fault will be ignored.
APPLICATION NOTE: If any of the External Diode 1, 2, or 3 channels are configured as a voltage input and
thermistor or other voltage source is used on the corresponding pins at device power up,
then the corresponding diode fault status bits will be set. The status bits should be cleared
prior to enabling the interrupts to avoid erroneous alert conditions.
6.13.1
Tcrit Status Register
The Tcrit Status Register stores the event that caused the SYS_SHDN# pin to be asserted. Each of
the temperature channels must be associated with the SYS_SHDN# pin before they can be set (see
Section 6.8). Once the SYS_SHDN# pin is asserted, it will be released when the temperature drops
below the threshold level however the individual status bit will not be cleared until read.
Bit 7 - HWS - This bit is set if the hardware set temperature channel meets or exceeds the temperature
threshold determined by the TRIP_SET voltage.
SMSC EMC2104
Revision 1.74 (05-08-08)
DATA5S9HEET
SMSC [ SMSC CORPORATION ]
