Dual RPM-Based PWM Fan Controller with Hardware Thermal Shutdown
Datasheet
6.8
Critical Temperature Limit Registers
Table 6.11 Limit Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
R/W
once
External Diode
1 Tcrit Limit
64h
(+100°C)
19h
1Ah
1Bh
1Ch
1Dh
Sign
64
32
16
8
4
2
1
R/W
once
External Diode
2 Tcrit Limit
64h
(+100°C)
Sign
Sign
Sign
Sign
64
64
64
64
32
32
32
32
16
16
16
16
8
8
8
8
4
4
4
4
2
2
2
2
1
1
1
1
R/W
once
External Diode
3 Tcrit Limit
64h
(+100°C)
R/W
once
External Diode
4 Tcrit Limit
64h
(+100°C)
R/W
once
Internal Diode
Tcrit Limit
64h
(+100°C)
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the
respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown
circuitry.
Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot
be updated again without a power on reset. Second, the respective temperature channel is linked to
the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the
measured temperature channel exceeds the Critical limit, the SYS_SHDN pin will be asserted, the
appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will
be set.
6.9
Configuration Register
Table 6.12 Configuration Register
ADDR
20h
R/W
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
Configuration MASK
-
-
SYS4
SYS3
SYS2
SYS1
APD
00h
The Configuration Register controls the basic functionality of the EMC2104. The bits are described
below. The Configuration Register is software locked.
Bit 7 - MASK - Blocks the ALERT# pin from being asserted.
‘0’ (default) - The ALERT# pin is unmasked. If any bit in either status register is set, the ALERT#
pins will be asserted (unless individually masked via the Mask Register)
‘1’ - The ALERT# pin is masked and will not be asserted.
Bit 4 - SYS4 - Enables the high temperature limit for the External Diode 4 channel to trigger the Critical
/ Thermal Shutdown circuitry (see Section 6.1). This bit is ignored if the DP3 / DN3 pins are configured
to measure a voltage input. In this case, the External Diode 4 channel is disabled and not compared
against any limits.
‘0’ (default) - the External Diode 4 channel high limit will not be linked to the SYS_SHDN# pin. If
the temperature exceeds the limit, the ALERT# pin will be asserted normally.
‘1’ - the External Diode 4 channel high limit will be linked to the SYS_SHDN# pin. If the temperature
exceeds the limit then the SYS_SHDN# pin will be asserted. The SYS_SHDN# pin will be released
SMSC EMC2104
Revision 1.74 (05-08-08)
DATA5S5HEET
SMSC [ SMSC CORPORATION ]
