High-Side Current-Sense and Internal 1°C Temperature Monitor
Datasheet
‘0’ - The Peak Detector circuitry will assert the ALERT pin when a current spike is detected. The
ALERT pin must be configured to operate in Comparator mode or it will not be asserted.
‘1’ (default) - The Peak Detector circuitry will assert the THERM pin when a current spike is
detected.
Bits 3 - 2 - V_QUEUE[1:0] - Determine the number of consecutive measurements that VSOURCE must
exceed the limits before flagging an interrupt.
Table 5.18 Voltage Queue Settings
V_QUEUE[1:0]
1
0
NUMBER OF CONSECUTIVE OUT-OF-LIMIT MEASUREMENTS
0
0
1
1
0
1
0
1
1 (default)
2
3
4
Bits 1-0 - V_AVG[1:0] - Controls the digital averaging that is applied to the source voltage
measurement, as shown in Table 5.19.
Table 5.19 Voltage Averaging Settings
V_AVG[1:0]
1
0
AVERAGING
0
0
1
1
0
1
0
1
Disabled (default)
2x
4x
8x
5.16 Current Sense Sampling Configuration Register
Table 5.20 Current Sense Sampling Configuration Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
51h
R/W
Current Sense
Sampling Config
CS_QUEUE
[1:0]
CS_SAMP_
AVG [1:0]
CS_SAMP_
TIME[1:0]
CS_RNG
[1:0]
03h
The Current Sense Sampling Configuration register stores the controls for determining the Current
Sense sampling / update time.
Bits 7 - 6 - CS_QUEUE[1:0] - Determine the number of consecutive measurements that the measured
VSENSE must exceed the limits before flagging an interrupt.
Revision 1.2 (09-27-10)
SMSC EMC1701
DATA3S8HEET
SMSC [ SMSC CORPORATION ]
