High-Side Current-Sense and Internal 1°C Temperature Monitor
Datasheet
The Low Limit Status Register contains the status bits that are set when a temperature or voltage
channel drops below the low limit. If any of these bits are set, the LOW status bit in the Status Register
is set. Reading from the Low Limit Status Register will clear all bits. Reading from the register will also
clear the LOW status bit in the Status Register if the error status has been removed.
If not masked, the ALERT pin will be set if the programmed number of consecutive alert counts have
been met and any of these status bits are set.
Once set, the status bits will remain set until read.
Bit 7 - VSENSE_LOW - This bit is set when the VSENSE value drops below its programmed low limit.
Bit 6 - VSRC_LOW - This bit is set when the VSOURCE value drops below its programmed low limit.
Bit 0 - ILOW - This bit is set when the Internal Diode channel drops below its programmed low limit.
5.14 Crit Limit Status Register
Table 5.16 Crit Limit Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
37h
R-C
Crit Limit
Status
VSENSE_
VCRIT
VSRC_
VCRIT
-
-
-
-
-
ITCRIT
00h
The Crit Limit Status register contains the status bits that are set when a temperature or voltage
channel Tcrit or Vcrit Limit is met or exceeded (see Section 5.9 and Section 5.23). If any of these bits
are set, the CRIT status bit in the Status register is set. Reading from the Crit Limit Status register will
not clear the status bits. Once the temperature drops below the Tcrit Limit minus the Tcrit Hysteresis,
the corresponding status bits will be automatically cleared. Once the voltage drops below the Vcrit Limit
minus the Vcrit Hysteresis, the corresponding status bits will be automatically cleared. The CRIT bit in
the Status register will be cleared when all individual bits are cleared.
Bit 7 - VSENSE_VCRIT - This bit is set when the VSENSE value meets or exceeds its programmed
Vcrit limit. When set, this bit will assert the THERM pin.
Bit 6 - VSRC_VCRIT- This bit is set when the VSOURCE value meets or exceeds its programmed Vcrit
limit. When set, this bit will assert the THERM pin.
Bit 0 - ITCRIT - This bit is set when the Internal Diode channel meets or exceeds its programmed Tcrit
limit. When set, this bit will assert the THERM pin.
5.15 Voltage Sampling Configuration Register
Table 5.17 Voltage Sampling Configuration Register
ADDR
50h
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
R/W
Voltage
Sampling
Config
PK_
ALERT_
THERM
-
-
-
V_QUEUE[1:0]
V_AVG[1:0]
80h
The Voltage Sampling Configuration register controls functionality for the source voltage measurement
and Peak Detector circuitry.
Bit 7 - PK_ALERT_THERM - Determines whether the ALERT pin or THERM pin is asserted if the Peak
Detector detects a current spike. If configured to assert the ALERT pin, the PEAK_MASK can block
the pin assertion normally. If configured to assert the THERM pin, it will not be masked.
SMSC EMC1701
Revision 1.2 (09-27-10)
DATA3S7HEET
SMSC [ SMSC CORPORATION ]
