High-Side Current-Sense and Internal 1°C Temperature Monitor
Datasheet
Table 5.28 PEAK_DET_DUR[3:0] Bit Decode (continued)
PEAK_DET_DUR[3:0]
PEAK DETECTION MINIMUM
DURATION
3
2
1
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
384.0ms
512.0ms
768.0ms
1024.0ms
1536.0ms
2048.0ms
3072.0ms
4096.0ms
5.18 Sense Voltage Registers
Table 5.29 Sense Voltage Registers
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
54h
R
Sense Voltage
High Byte
Sign
1024
512
256
128
64
32
16
00h
55h
R
Sense Voltage
Low Byte
8
4
2
1
00h
The Sense Voltage registers store the measured VSENSE voltage across the sense resistor (RSENSE
)
placed between the SENSE+ and SENSE- pins (see Section 4.1.1, "Current Measurement"). Note that
the bit weighting values are for representation of the voltage relative to full scale. There is no internal
scaling of data and all normal binary bit weightings still apply.
The Sense Voltage register data format is standard 2’s complement format with the positive full scale
value (7F_Fh) and negative full scale value (80_0h) equal to the programmed maximum sense voltage
(see Section 5.16, "Current Sense Sampling Configuration Register").
The Sign bit indicates the direction of current flow. If the Sign bit is ‘0’, current is flowing through
RSENSE from the SENSE+ pin to the SENSE- pin. If the Sign bit is ‘1’, the current is flowing through
RSENSE from the SENSE- pin to the SENSE+ pin. See Section 4.1.1, "Current Measurement" for
examples.
Table 5.30 VSENSE Data Format
VSENSE
BINARY
HEX (AS READ BY REGISTERS)
Minus Full Scale
-2 LSB
1000_0000_0000
1111_1111_1110
1111_1111_1111
0000_0000_0000
80_0h
FF_Eh
FF_Fh
00_0h
-1 LSB
Zero
Revision 1.2 (09-27-10)
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