High-Side Current-Sense and Internal 1°C Temperature Monitor
Datasheet
Bits 3-1 - CALRT[2:0] - Determines the number of consecutive measurements that must have an out-
of-limit condition before the ALERT pin is asserted. The bits are decoded as shown in Table 5.13. The
default setting is 1 consecutive out-of-limit conversion.
Table 5.13 Consecutive ALERT / THERM Settings
NUMBER OF CONSECUTIVE OUT-OF-LIMIT
2
1
0
MEASUREMENTS
0
0
0
1
(default for CALRT[2:0])
0
0
1
0
1
1
1
1
1
2
3
4
(default for CTHRM[2:0])
5.12 High Limit Status Register
Table 5.14 High Limit Status Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
35h
R-C
High Limit
Status
VSENSE_
HIGH
VSRC_
HIGH
-
-
-
-
-
I
00h
HIGH
The High Limit Status Register contains the status bits that are set when a temperature or voltage
channel high limit is met or exceeded. If any of these bits are set, the HIGH status bit in the Status
Register is set. Reading from the High Limit Status Register will clear all bits if the error condition has
been removed. Reading from the register will also clear the HIGH status bit in the Status Register if
the error condition has been removed.
If not masked, the ALERT pin will be set if the programmed number of consecutive alert counts have
been met and any of these status bits are set. Once set, the status bits will remain set until read unless
the ALERT pin is configured as a comparator output (see Section 4.4.2).
Bit 7 - VSENSE_HIGH - This bit is set when the VSENSE value meets or exceeds its programmed high
limit.
Bit 6 - VSRC_HIGH - This bit is set when the VSOURCE value meets or exceeds its programmed high
limit.
Bit 0 - IHIGH - This bit is set when the Internal Diode channel meets or exceeds its programmed high
limit.
5.13 Low Limit Status Register
Table 5.15 Low Limit Status Register
ADDR
36h
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
R-C
Low Limit
Status
VSENSE_
LOW
VSRC_
LOW
-
-
-
-
-
ILOW
00h
Revision 1.2 (09-27-10)
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