High-Side Current-Sense and Internal 1°C Temperature Monitor
Datasheet
The Channel Mask Register controls individual channel masking. When a channel is masked, the
ALERT pin will not be asserted when the masked channel reads an out-of-limit error. The channel
mask does not mask the THERM pin.
Bit 7 - VSENSE_MASK - Masks the ALERT pin from asserting when the VSENSE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
‘0’ (default) - The VSENSE voltage channel will cause the ALERT pin to be asserted (if enabled).
‘1’ - The VSENSE voltage channel will not cause the ALERT pin to be asserted (if enabled).
Bit 6 - VSRC_MASK - Masks the ALERT pin from asserting when the VSOURCE value meets or
exceeds the high limit or drops below the low limit. This bit will have no effect on the THERM pin
functionality.
‘0’ (default) - The VSOURCE voltage channel will cause the ALERT pin to be asserted (if enabled).
‘1’ - The VSOURCE voltage channel will not cause the ALERT pin to be asserted (if enabled).
BIt 5 - PEAK_MASK - Masks the ALERT pin from asserting when the Peak Detector circuitry detects
a current spike. This bit will have no effect on the THERM pin functionality.
‘0’ (default) - The Peak Detector circuitry will cause the ALERT pin to be asserted (if enabled).
‘1’ - The Peak Detector circuitry will not cause the ALERT pin to be asserted (if enabled).
Bit 0 - INTMASK - Masks the ALERT pin from asserting when the Internal Diode temperature is out-
of-limit.
‘0’ (default) - The Internal Diode channel will cause the ALERT pin to be asserted if it is out-of-limit.
‘1’ - The Internal Diode channel will not cause the ALERT pin to be asserted if it is out-of-limit.
5.11 Consecutive Alert Register
Table 5.12 Consecutive Alert Register
ADDR
R/W
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
22h
R/W
Consecutive
Alert
TIME
OUT
CTHRM[2:0]
CALRT[2:0]
-
70h
The Consecutive Alert Register determines how many times an out-of-limit error must be detected in
consecutive measurements before the interrupt status registers are asserted. This applies to
temperature limits only. The voltage measurement and current sense measurements are controlled via
the Voltage Channel Configuration register and Current Sense Configuration register respectively (see
Section 5.15 and Section 5.16).
When the ALERT pin is configured as a comparator, the consecutive alert counter will ignore low limit
errors and only increment if the measured temperature meets or exceeds the High Limit.
Bit 7 - TIMEOUT - Determines whether the SMBus Timeout function is enabled.
‘0’ (default) - The SMBus Timeout feature is disabled. The SMCLK line can be held low indefinitely
without the device resetting its SMBus protocol.
‘1’ - The SMBus Timeout feature is enabled. If the SMCLK line is held low for more than 30ms,
the device will reset the SMBus protocol.
Bits 6-4 - CTHRM[2:0] - Determines the number of consecutive measurements that must exceed the
corresponding Tcrit Limit before the THERM pin is asserted.
SMSC EMC1701
Revision 1.2 (09-27-10)
DATA3S5HEET
SMSC [ SMSC CORPORATION ]
