Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Appendix B High-Performance 8051 Extended
Interrupt Unit
B.1
Interrupts
The EXIF, EICON, EIE, and EIP registers provide flags, enable control, and priority control for the
extended interrupt unit in the LPC47N350 high-performance 8051.
B.1.1
Interrupt Processing
When an enabled interrupt occurs, the CPU vectors to the address of the interrupt service routine (ISR)
associated with that interrupt (See Table 7.15 on page 66). The CPU executes the ISR to completion
unless another interrupt of higher priority occurs. Each ISR ends with a RETI (return from interrupt)
instruction. After executing the RETI, the CPU returns to the next instruction that would have been
executed if the interrupt had not occurred.
An ISR can only be interrupted by a higher priority interrupt. That is, an ISR for a low-level interrupt can
only be interrupted by high-level interrupt. An ISR for a high-level interrupt can only be interrupted by
the power-fail interrupt (extended interrupt unit only).
The 8051 always completes the instruction in progress before servicing an interrupt. If the instruction in
progress is RETI, or a write access to any of the IP, IE, EIP, or EIE SFRs, the 8051 completes one
additional instruction before servicing the interrupt.
B.1.2
B.1.3
Interrupt Masking
The EA bit in the IE SFR (IE.7) is a global enable for all interrupts except the power-fail interrupt. When
EA = 1, each interrupt is enabled/masked by its individual enable bit. When EA = 0, all interrupts are
masked. The only exception is the power-fail interrupt, which is not affected by the EA bit. When EPFI
= 1, the power-fail interrupt is enabled, regardless of the state of the EA bit. Table 7.15 on page 66
provides a summary of interrupt sources, flags, enables, and priorities.
Interrupt Priorities
There are two stages of interrupt priority assignment, interrupt level and natural priority. The interrupt
level (highest, high, or low) takes precedence over natural priority. The power-fail interrupt, if enabled,
always has highest priority and is the only interrupt that can have highest priority. All other interrupts
can be assigned either high or low priority.
In addition to an assigned priority level (high or low), each interrupt also has a natural priority, as listed
in Table 7.15 on page 66. Simultaneous interrupts with the same priority level (for example, both high)
are resolved according to their natural priority. For example, if int0_n and int2 are both programmed as
high priority, int0_n takes precedence.
Once an interrupt is being serviced, only an interrupt of higher priority level can interrupt the service
routine of the interrupt currently being serviced.
B.1.4
Interrupt Sampling
The internal timers and serial ports generate interrupts by setting their respective SFR interrupt flag bits.
External interrupts are sampled once per instruction cycle.
int0_n and int1_n are both active low and can be programmed to be either edge-sensitive or level-
sensitive, through the IT0 and IT1 bits in the TCON SFR. For example, when IT0 = 0, int0_n is level-
sensitive and the 8051 sets the IE0 flag when the int0_n pin is sampled low. When IT0 = 1, int0_n is
edge-sensitive and 8051 sets the IE0 flag when the int0_n pin is sampled high then low on consecutive
samples.
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