Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 20.1 LPC47N350 GPIO Types (continued)
REGISTER
CONTROL
GROUP
WAKE
BUFFER
MODES
PIN NAMES
CAPABLE
TYPE
(Note 20.7)
(Note 20.1)
(Note 20.2) (Note 20.3)
21
22
23
24
25
26
27
28
29
30
31
8051 (non-SFR)
Group B
GPIO8 (WK_SE12)/RXD
GPIO9 (WK_SE13)/TXD
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
OD
GPIO10 (WK_SE14)
GPIO11 (WK_SE15)/AB2A_DATA
GPIO12 (WK_SE16)/AB2A_CLK
GPIO13 (WK_SE17)/AB2B_DATA
GPIO14 (WK_SE20)/AB2B_CLK
GPIO15 (WK_SE21)/FAN_TACH1
GPIO16 (WK_SE22)/FAN_TACH2
GPIO17 (WK_SE23)/A20M
8051 (non-SFR)
Group C
KSO13/GPIO18 (WK_SE27)
(Note 20.4)
32
33
34
35
36
37
38
39
40
41
42
GPIO19 (WK_SE24)
GPIO20 (WK_SE25)/PS2CLK
GPIO21 (WK_SE26)/PS2DAT
LGPIO50
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
PP
OD
OD
LPC/8051
Group G
Group H
PP
(See Note 20.6)
LGPIO51
PP
LGPIO52
PP
LGPIO53
PP
LPC/8051
LGPIO60
PP/OD
PP/OD
PP/OD
PP/OD
(See Note 20.6)
LGPIO61
LGPIO62
LGPIO63
Note 20.1 The pin names for the pins are organized by primary pin function listed first. The alternate
functions on the pin are separated by “/” (backslash).
Note 20.2 All non-SFR GPIOs that are wakeup capable can be configured for low-to-high, high-to-high,
or either-edge wakeup. All alternate functions of wake-capable GPIO primary function pins
can generate wake events.
Note 20.3 The buffer modes apply only to the GPIOs. PP = Push-Pull (Totem Pole) Outputs; PP/OD =
Selectable Push-Pull or Open-Drain Outputs.
Note 20.4 The OUT8/KBRST functions are on KSO12/OUT8/KBRST pin and OUT8/KBRST pin.
Note 20.5 GPIO3 can be enabled to directly generate 8051 INT1.
Note 20.6 These pins can be controlled by the LPC Host or the 8051
Revision 1.1 (01-14-03)
218
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
