Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
19.4
FAN1 Read Latch Register
The FAN1 read latch register (Table 19.3) stores the maximum last fan pulse counter value before the
rising edge of the next FAN1 tachometer input pulse. The fan pulse count is computed from the
equation in Table 19.1. The FAN1 read latch register value may not be valid for up to 2 fan tachometer
input pulses following a write to the preload register.
Table 19.3 FAN1 Read Latch Register
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F9B
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
D6
R
D6
R
D6
R
D3
R
D2
R
D1
R
D0
D7
19.5
FAN2 Read Latch Register
The FAN2 read latch register (Table 19.4) stores the last (maximum) fan pulse counter value before the
rising edge of the FAN2 tachometer input pulse. The fan pulse count is computed from the equation in
Table 19.1. The FAN2 read latch register value may not be valid for up to 2 fan tachometer input pulses
following a write to the preload register.
Table 19.4 FAN2 Read Latch Register
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F9C
VCC1
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
D6
R
D6
R
D6
R
D3
R
D2
R
D1
R
D0
D7
Revision 1.1 (01-14-03)
214
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
