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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
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Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
19.2.2 Fan Pulse Counter and Read Latch  
The fan pulse counter measures the fan pulse time, T shown in Figure 19.1. The fan pulse counter is  
p,  
reset by the rising edge of each fan tachometer input pulse and by writing the counter preload register.  
The fan pulse counter does not wrap. For example, when the counter reaches 0xFF, it remains at 0xFF  
until the counter is reset by the next input pulse or by writing the Preload register. The host can read  
the last maximum fan pulse counter value using the FAN1 and FAN2 Read Latch registers (see Section  
19.3, "Example" and Section 19.4, "FAN1 Read Latch Register", below). The fan pulse counter equation  
is shown in Table 19.1. The factor of ½ in first term of the equation accounts for the fan Revolution  
Time T (i.e., two pulses per revolution as shown in Figure 19.1). The numerator of the second term  
R
is derived by multiplying the 32.768kHz timebase by 60sec/min. The denominator of the second term  
is the product of the fan RPM and the timebase prescaler.  
19.2.3 Fan Pulse Counter Threshold Detector  
The fan pulse counter threshold detector consists of the two AND’ed MSB outputs of the fan pulse  
counter. This corresponds to an upper limit for the fan pulse counter of 192. The outputs of the fan  
pulse counter threshold detectors are always asserted when the fan pulse count equals or exceeds 192.  
The outputs of the fan pulse counter threshold detectors are always deasserted when the fan pulse  
count is less than 192. If enabled, the 8051 receives an interrupt when the outputs of the fan pulse  
counter threshold detectors are asserted. For a description of the FAN TACH1 and FAN TACH2 8051  
interrupt registers see Section 19.9, "8051 FAN Tachometer Interrupt Registers".  
Table 19.1 Fan Pulse Counter Equation  
6
FAN PULSE COUNT =  
1
2
X
1.966 x 10  
RPM x PRESCALER  
19.2.4 Fan Pulse Counter Preload  
The fan pulse counter preload is the initial value for the fan pulse counter which is used to scale the  
count so that the value of 192 corresponds to the “lower limit” of the threshold RPM. The fan pulse  
counter is initialized with the preload on the rising edge of the fan tachometer input pulse. Typically, the  
fan pulse counter preload value will be 192 minus the fan pulse count of the desired RPM trigger  
threshold. The counter preload value is programmable for each fan tachometer via the FAN1 and FAN2  
Preload Registers (see Section 19.5, "FAN2 Read Latch Register" and Section 19.7, "FAN2 Preload  
Register"). By setting the fan pulse counter preload value and the timebase prescaler appropriately, the  
8051 can be interrupted when the fan speed reaches the desired percentage of the nominal RPM to  
indicate fan failures for a wide range of fan types and speeds (see Section 19.3, "Example").  
Revision 1.1 (01-14-03)  
212  
SMSC LPC47N350  
DATASHEET  
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