Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Chapter 11 Watch Dog Timer
11.1
WDT Operation
When enabled, the Watch Dog Timer (WDT) circuit will generate a system reset if the user program fails
to reload the watchdog timer (WDT) within a specified length of time known as the ‘watchdog interval’.
The WDT consists of an 8-bit timer (WDT) with a 9-bit prescaler. The prescaler is fed with 32 KHz
which always runs, even if the 8051 is in SLEEP state. The 8 bit WDT timer is decremented every
(1/32KHz) *512 seconds or 16.0 ms. Thus, the watchdog interval is programmable between 16ms and
4.08 seconds on 16ms intervals.
11.2
WDT Action
If the 8 bit timer (WDT) underflows, a VCC1 POR is generated.
8051 in Idle Mode - WDT will be active if enabled. When the WDT timer underflows in idle mode, the
8051 will be reset. It is up to the firmware engineer to design code that uses a timer to generate an
interrupt that will exit idle mode and re-initialize the WDT timer and then put the 8051 back into idle
mode.
8051 in Sleep Mode - If enabled, the WDT is active since it is running off of the 32 KHz clock.
Therefore, if the WDT is enabled, the 8051 should never remain in the SLEEP state for more than 4
seconds.
11.3
11.4
WDT Activation
Upon VCC1 POR, the Watch Dog Timer powers up inactive. The Watch Dog Timer is activated when
the WDT enable bit (WDT CONTROL bit D1) is set by 8051 firmware. The WDT may be disabled under
software control through a specific sequence. Software can clear the SDT enable bit by:
■
Setting the WLE (WDT Load enable) bit in the WDT Control/Status Register.
■
Writing 00h to the WDT Timer Register (this causes the WDT Enable and the WLE bits to each reset
to 0).
Once the WDT has been activated, this sequence must be executed in order to disable watchdog
operation via software control.
Note: Since a VCC1 POR will reset the WDT enable bit, the WDT must be re-enabled after each
occurrence.
WDT Reset Mechanism
The watchdog timer (WDT) must be reloaded within periods that are shorter than the programmed
watchdog interval; otherwise the WDT will underflow and a VCC1 POR will be generated. It is the
responsibility of the user program to continually execute sections of code which reload the 8 bit timer
(WDT).
The WDT is reloaded in two stages in order to prevent erroneous software from reloading the watchdog.
First, bit D0 (WLE) in the WDT CONTROL register must be set. Then, the WDT may be loaded. When
the WDT is loaded, WLE is automatically reset. WDT can not be loaded when WLE is reset. Since
the WDT timer is a down counter, a reload value of 01h results in the minimum WDT interval (16ms)
and a reload value of 0FFh results in the maximum WDT interval (4.08 seconds). Loading 00h into the
WDT disables the WDT and clears the WDT_EN bit.
Note: The 9 bit prescaler is initialized whenever the WDT timer is loaded.
SMSC LPC47N350
133
Revision 1.1 (01-14-03)
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