Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
11.5
WDT Memory Mapped Registers
Table 11.1 WDT
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x 7F38
VCC1
0xFF
DEFAULT
D7
D6
R/W
D5
R/W
D4
R/W
D3
R/W
D2
R/W
D1
R/W
D0
R/W
R/W
8051 R/W
SYSTEM R/W
BIT DEF
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WDT Timer
Table 11.2 WDT Control/Status
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x 7F37
VCC1
0x00
DEFAULT
D7-D2
D1
D0
R
R/W
N/A
R/W
N/A
8051 R/W
N/A
SYSTEM R/W
Reserved
WDT
WLE
BIT DEF
Enable
WLE (WDT Load Enable)
Watchdog Load Enable bit must be set to enable writing to the WDT Timer register. This bit is
automatically reset when the 8051 writes to the WDT register. If this bit is reset, writes to the WDT
register are ignored.
WDT_EN
The WDT enable bit must be set by 8051 firmware to enable or start the Watch Dog Timer. A VCC1
POR or the above described software sequence will reset this bit.
Revision 1.1 (01-14-03)
134
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
