Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Chapter 12 8051 System Power Management
The High-Performance 8051 core provides support for two further power-saving modes, available when
inactive: idle mode, typically entered between keystrokes; and sleep mode, entered upon command from
the host. The High Performance 8051 is wakeable from sleep mode through a set of external and
internal events called Wake-Up events. The events are listed in Table 12.1. When exiting the Sleep
mode, the High Performance 8051 will continue executing code from where it left off when put into sleep
with no changes to the SFR and pins.
The LPC47N350 is fully static and will pickup from where it left off in the event of a wake-up event.
12.1
Idle Mode
Entering IDLE mode: Idle mode is initiated by an instruction that sets the PCON.0 bit (SFR address
87H) in the keyboard. In idle mode, the internal clock signal to the keyboard CPU is gated off, but not
to the Interrupt Timer and Serial Port functions. The CPU status is preserved in its entirety: The Stack
Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their
data. The port pins hold the logical levels they had when Idle mode was activated.
System fully powered
up and running.
RESET_OUT=low, 8051STP_CLK=0.
8051 owns Flash interface,
running keyboard code.
The host either issues a user-
defined command to put the
8051into idle mode, or the
8051 code determines that
the 8051 should enter
Idle mode.
SLEEPFLAG = 0
PCON.0 = 1
8051 now in Idle mode,
8051 clock running.
Figure 12.1 Entering Idle Mode
SMSC LPC47N350
137
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
