ST7578
(VDD = 1.8V , Ta =-30~85°C)
Item
Signal
Symbol
tSCYC
tSHW
tSLW
tSAS
Condition
Min.
280
140
140
50
Max.
—
Unit
Serial clock period
SCLK “H” pulse width
SCLK “L” pulse width
Address setup time
Address hold time
Data setup time
SCLK
—
—
—
A0
ns
tSAH
tSDS
tSDH
tCSS
tCSH
150
50
—
—
SDA
CSB
Data hold time
50
—
CSB-SCLK time
40
—
CSB-SCLK time
180
—
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD1 as the standard.
Ver 1.2
42/52
2007/04/30