ST7578
(VDD = 1.8V , Ta =-30~85°C)
Item
Signal
Symbol
tAW8
Condition
Min.
150
30
Max.
—
Unit
Address setup time
A0
Address hold time
tAH8
—
System cycle time
tCYC8
tCCLW
tCCHW
tCCLR
tCCHR
tDS8
550
170
150
170
150
120
30
—
/WR
RD
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Data hold time
READ access time
—
—
ns
—
—
—
tDH8
D[7:0]
—
tACC8
tOH8
CL = 16 pF
CL = 16 pF
240
200
READ Output disable time
10
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD1 as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
Ver 1.2
38/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
