ST7578
(VDD = 1.8V , Ta =-30~85°C)
Item
Signal
Symbol
tAW6
Condition
Min.
150
30
Max.
—
Unit
Address setup time
A0
Address hold time
tAH6
—
System cycle time
tCYC6
tEWLW
tEWHW
tEWLR
tEWHR
tDS6
440
170
150
170
150
180
30
—
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
Write data setup time
—
E
—
ns
—
—
—
Write data hold time
tDH6
—
D[7:0]
—
Read data access time
Read data output disable time
tACC6
tOH6
CL = 16 pF
CL = 16 pF
240
200
10
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≦ (tCYC6 – tEWLW – tEWHW) for (tr + tf) ≦ (tCYC6 – tEWLR – tEWHR) are specified.
*2 All timing is specified using 20% and 80% of VDD1 as the reference.
*3 tEWLW and tEWLR are specified as the overlap between CSB being “L” and E.
Ver 1.2
40/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
