ST7578
SERIAL INTERFACE (4-Line Interface)
First bit
Last bit
(VDD = 3.3V , Ta =-30~85°C)
Item
Serial clock period
Signal
Symbol
tSCYC
tSHW
tSLW
tSAS
Condition
Min.
Max.
—
Unit
120
60
SCLK
SCLK “H” pulse width
SCLK “L” pulse width
Address setup time
Address hold time
Data setup time
—
60
—
20
—
A0
ns
tSAH
tSDS
tSDH
tCSS
tCSH
90
—
20
—
SDA
CSB
Data hold time
10
—
CSB-SCLK time
20
—
CSB-SCLK time
120
—
(VDD = 2.8V , Ta =-30~85°C)
Item
Serial clock period
SCLK “H” pulse width
SCLK “L” pulse width
Address setup time
Address hold time
Data setup time
Signal
Symbol
tSCYC
tSHW
tSLW
tSAS
Condition
Min.
200
100
100
30
Max.
—
Unit
SCLK
—
—
—
A0
ns
tSAH
tSDS
tSDH
tCSS
tCSH
120
30
—
—
SDA
CSB
Data hold time
20
—
CSB-SCLK time
30
—
CSB-SCLK time
150
—
Ver 1.2
41/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
