ST7578
SERIAL INTERFACE (3-Line Interface)
First bit
Last bit
(VDD = 3.3V , Ta =-30~85°C)
Item
Serial clock period
Signal
Symbol
tSCYC
tSHW
tSLW
Condition
Condition
Condition
Min.
Max.
—
Unit
120
60
SCLK
SCLK “H” pulse width
SCLK “L” pulse width
Data setup time
—
60
—
ns
tSDS
20
—
SDA
CSB
Data hold time
tSDH
tCSS
10
—
CSB-SCLK time
CSB-SCLK time
20
—
tCSH
130
—
(VDD = 2.8V , Ta =-30~85°C)
Item
Serial clock period
SCLK “H” pulse width
SCLK “L” pulse width
Data setup time
Signal
Symbol
tSCYC
tSHW
tSLW
Min.
180
90
Max.
—
Unit
SCLK
—
90
—
ns
tSDS
30
—
SDA
CSB
Data hold time
tSDH
tCSS
20
—
CSB-SCLK time
30
—
CSB-SCLK time
tCSH
160
—
(VDD = 1.8V , Ta =-30~85°C)
Item
Serial clock period
SCLK “H” pulse width
SCLK “L” pulse width
Data setup time
Signal
Symbol
tSCYC
tSHW
tSLW
Min.
240
120
120
60
Max.
—
Unit
SCLK
—
—
ns
tSDS
—
SDA
CSB
Data hold time
tSDH
tCSS
50
—
CSB-SCLK time
40
—
CSB-SCLK time
tCSH
190
—
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD1 as the standard.
Ver 1.2
43/52
2007/04/30
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
