ST7578
Power-Save Flow and Sequence
ENTERING THE POWER SAVE MODE
The power save mode is achieved by setting PD bit to be “1”. No specified instruction flow required.
EXITING THE POWER SAVE MODE
INTERNAL SEQUENCE of EXIT POWER SAVE MODE
After receiving “PD=0”, the internal circuits (Power) will starts the following procedure.
Note:
1.
2.
The power stable time is determined by LCD panel loading.
The power stable time in this figure is base on: LCD Panel Size = 1.4” with C1=1uF, C2=1uF.
Ver 1.2
34/52
2007/04/30