ST2202A
TABLE 11-3 LCD Clock Control Register (LCKR)
Address Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
$048 LCKR
Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
LMODꢀ LCK[3]ꢀ LCK[2]ꢀ LCK[1]ꢀ LCK[0]ꢀ ꢁꢀꢁꢀꢁ0ꢀ0000ꢀ
ꢀ
Bitꢀ4:ꢀ ꢀ LMODꢀ:ꢀLCDꢀdataꢀbusꢀmodeꢀselectionꢀ
ꢀ=ꢀ1ꢁbitꢀmodeꢀ
0
1ꢀ=ꢀ4ꢁbitꢀmodeꢀ
ꢀ
Bitꢀ3~0:ꢀLCKR[3:0]ꢀ:ꢀLCDꢀclockꢀselectionꢀ
LCDCKꢀ
LCKR[3:0]
1ꢁbitꢀmodeꢀ
LMOD )ꢀ
4ꢁbitꢀmodeꢀ
(
=
0
(
LMOD=1)ꢀ
OSCKꢀ
OSCK/2ꢀ
/4ꢀ
0000
0001ꢀ
0010ꢀ
0011ꢀ
0100ꢀ
0101ꢀ
0110ꢀ
0111ꢀ
1000ꢀ
1001ꢀ
1010ꢀ
1011ꢀ
1100ꢀ
1101ꢀ
1110ꢀ
1111ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
OSCKꢀ
/6ꢀ
/8ꢀ
/10ꢀ
/12ꢀ
/14ꢀ
/16ꢀ
/18ꢀ
/20ꢀ
/22ꢀ
/24ꢀ
/26ꢀ
/28ꢀ
OSCK/2ꢀ
OSCK/4ꢀ
OSCK/6ꢀ
/30ꢀ
ꢀ
ꢀ
TABLE 11-4 PSG Control Register (PSGC)
Address Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
ꢁꢀ
ꢁꢀ
PCK[2]ꢀ PCK[1]ꢀ PCK[0]ꢀ PRBSꢀ
PCK[2]ꢀ PCK[1]ꢀ PCK[0]ꢀ DMD[1]ꢀ DMD[0]ꢀ
C1ENꢀ
C0ENꢀ DACE=0ꢀ ꢁ000ꢀ0000ꢀ
INHꢀ DACE=1ꢀ ꢁ000ꢀ0000ꢀ
$016 PSGC
R/Wꢀ
ꢀ
Bitꢀ3~0:ꢀPSGC[6:4]ꢀ:ꢀPSGꢀclockꢀselectionꢀ
PCK[2:0]
000
PSGCKꢀ
SYSCK/2ꢀ
SYSCK/4ꢀ
SYSCK/8ꢀ
SYSCK/16ꢀ
SYSCKꢀ
001ꢀ
010ꢀ
011ꢀ
1xxꢀ
111ꢀ
CLK32ꢀ
ꢀ
ꢀ
TABLE 11-5 BGR Control Register (BCTR)
Address Name
R/W
Bit 7
Bit 6
ꢁꢀ
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
$063 BCTR
R/Wꢀ
TESTꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
BSTRꢀ BMODꢀ BGRENꢀ 0ꢁꢀꢁꢀꢁꢀꢁ000ꢀ
ꢀ
Bitꢀ7:ꢀTESTꢀ:ꢀTestꢀbit,ꢀmustꢀbeꢀ“0”ꢀ
ꢀ
Bitꢀ2:ꢀBSTRꢀ:ꢀModulationꢀstrengthꢀselectionꢀbitꢀ
ꢀ=ꢀFullꢀmodulationꢀstrength (recommended)
1ꢀ=ꢀHalfꢀmodulationꢀstrengthꢀ
0
ꢀ
ꢀ
Bitꢀ1:ꢀBMODꢀ:ꢀModulationꢀmodeꢀselectionꢀbitꢀ
ꢀ=ꢀCoarseꢀmodulationꢀmodeꢀ
1ꢀ=ꢀFineꢀmodulationꢀmodeꢀ(recommended)
0
ꢀ
ꢀ
Bitꢀ0:ꢀBGRENꢀ:ꢀBGRꢀenable/disableꢀbitꢀ
ꢀ=ꢀDisableꢀBGRꢀ
1ꢀ=ꢀEnableꢀBGRꢀ
0
ꢀ
Verꢀ2.5ꢀ
23
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
