ST2202A
ꢀ
ꢀ
Integer
Divider
BGR
BSR[7:0] / BCTR[2:0]
Target
IN
÷N
BGRCK
OUT
OUT
IN
CLK32xK
REF
BDIV[7:0]
OSCK
‧
‧
SPICK
Divider
SPICK
IN
OUT
OSCK/2/4/8…/256
PSGCK
Divider
SCKR[6:4]
INA
PSGCK
‧
‧
OUT
INB
OSCKx2,OSCK/2/4/8/16
CLK32
LCDCK
Divider
PSGC[6:4]
LCDCK
OUT
‧
IN
OUT
OSCK,OSCK/2/4…/30
OSC
OSTP(SYS[6])
EN
LCKR[4:0]
MUX2
SYSCK
IN0
IN1
XBAK(SYS[4])
XSTP(SYS[5])
OSCK, CLK32
Heavy
OUT
‧
Normal
SEL
Warm-up control
OSCX
256 cycles
16 cycles
WSKP(SYS[3])
EN
XSEL(SYS[7])
XSEL(SYS[7])
CLK32
ꢀ
FIGURE 11-1 Clock Generator Diagram
ꢀ
ꢀ
TABLE 11-2 System Control Register (SYS)
Address Name R/W
Bit 7
XSELꢀ
XSELꢀ
Bit 6
OSTPꢀ
OSTPꢀ
Bit 5
XSTPꢀ
XSTPꢀ
Bit 4
Bit 3
WSKPꢀ WAITꢀ IRRENꢀ HIGHꢀ
WSKPꢀ WAITꢀ IRRENꢀ LVDENꢀ 0000ꢀ0000ꢀ
Bit 2
Bit 1
Bit 0
Default
0000ꢀ0001ꢀ
Rꢀ
$030 SYS
ꢁꢀ
Wꢀ
ꢀ
Bitꢀ7:ꢀ ꢀ XSEL :ꢀWrite:ꢀSelectꢀsourceꢀofꢀsystemꢀclockꢀ(SYSCK)ꢀ/ꢀRead:ꢀreportꢀofꢀclockꢀsourceꢀbeingꢀusedꢀ
0ꢀ=ꢀOSCꢀ
1ꢀ=ꢀOSCXꢀ
ꢀ
ꢀ
ꢀ
Bitꢀ6:ꢀ ꢀ OSTP :ꢀOSCꢀstopꢀcontrolꢀbitꢀ
0ꢀ=ꢀEnableꢀOSCꢀ
1ꢀ=ꢀDisableꢀOSCꢀ
Bitꢀ5:ꢀ ꢀ XSTP :ꢀOSCXꢀstopꢀcontrolꢀbitꢀ
0ꢀ=ꢀEnableꢀOSCXꢀ
1ꢀ=ꢀDisableꢀOSCXꢀ
Bitꢀ4:ꢀ ꢀ No used : Pleaseꢀkeepꢀthisꢀbitꢀ“0”.ꢀ
ꢀ
Bitꢀ3:ꢀ ꢀ WSKP :ꢀSystemꢀwarmꢁupꢀcyclesꢀselectionꢀbitꢀ
0ꢀ=ꢀ256ꢀwarmꢁupꢀcyclesꢀ
1ꢀ=ꢀ16ꢀwarmꢁupꢀcyclesꢀ
ꢀ
Verꢀ2.5ꢀ
22
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
