ST2202A
11. CLOCK GENERATOR
TheꢀST2202ꢀhasꢀtwoꢀoscillatorsꢀOSCꢀandꢀOSCXꢀforꢀbothꢀ
highꢀandꢀlowꢀfrequencyꢀneeded.ꢀWhenꢀoscillatorꢀmodeꢀ
selectionꢀpin,ꢀXMD,ꢀisꢀinputtedꢀhighꢀlevel,ꢀtheꢀhighꢀ
frequencyꢀoscillatorꢀOSCꢀadoptsꢀonlyꢀoneꢀexternalꢀresistorꢀ
toꢀgenerateꢀaꢀhighꢀfrequencyꢀclockꢀOSCKꢀwhichꢀisꢀusedꢀbyꢀ
almostꢀeveryꢀblockꢀinꢀchip.ꢀOSCꢀcanꢀalsoꢀchangeꢀtoꢀbeꢀaꢀ
resonator/crystalꢀoscillatorꢀbyꢀinputꢀlowꢀlevelꢀtoꢀXMD.ꢀ
ꢀ
TheꢀlowꢀfrequencyꢀoscillatorꢀOSCXꢀneedsꢀaꢀ32768Hzꢀ
crystalꢀandꢀoneꢀcapacitorꢀtoꢀgeneratorꢀaꢀpreciseꢀfrequencyꢀ
CLK32ꢀforꢀBaseꢀtimer,ꢀTimer1ꢀandꢀtheꢀreferenceꢀclockꢀofꢀ
baudꢀrateꢀgeneratorꢀ(BGR).ꢀ
enoughꢀbaseꢀfrequencyꢀandꢀtoꢀkeepꢀitꢀunchanged.ꢀBitsꢀofꢀ
PSGC[6:4]ꢀcontrolꢀtheꢀoptionsꢀofꢀPSGCK.ꢀReferꢀtoꢀTABLEꢀ
11ꢁ4ꢀforꢀtheseꢀoptions.ꢀ
ꢀ
ꢀ
BGRCK
TheꢀST2202ꢀequipsꢀaꢀbaudꢀrateꢀgeneratorꢀ(BGR),ꢀwhichꢀisꢀ
controlledꢀbyꢀBGRꢀcontrolꢀregisterꢀBCTR,ꢀlockedꢀfrequencyꢀ
selectionꢀregisterꢀBRS,ꢀandꢀdividerꢀcontrolꢀregisterꢀBDIV.ꢀ
TheꢀBGRꢀutilizesꢀdigitalꢀPLLꢀtechniqueꢀtoꢀlockꢀaꢀhighꢀ
frequencyꢀ
ꢀ aroundꢀOSCK/2.ꢀThisꢀhighꢀfrequencyꢀisꢀ
FHIGH
furtherꢀscaledꢀdownꢀviaꢀanꢀintegerꢀdividerꢀtoꢀaꢀdesiredꢀ
frequencyꢀBGRCK.ꢀTheꢀBGRꢀusesꢀCLK32ꢀasꢀreferenceꢀ
clockꢀforꢀtheꢀmodulationꢀofꢀOSCK.ꢀThereꢀareꢀtwoꢀ
ꢀ
OtherꢀclocksꢀareꢀsourcedꢀfromꢀeitherꢀOSCKꢀorꢀCLK32ꢀandꢀ
areꢀlistedꢀbelow:ꢀ
ꢀ
modulationꢀmodesꢀwhichꢀcanꢀbeꢀselectedꢀbyꢀBMOD
ꢀ
(BCTR[1]).ꢀTheꢀmodulationꢀstrengthꢀisꢀalsoꢀcontrollableꢀbyꢀ
settingꢀorꢀresettingꢀBSTRꢀ(BCTR[2]).ꢀ ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Systemꢀclock:ꢀ ꢀ SYSCK
LCDꢀcontrollerꢀclock:ꢀ ꢀ LCDCK
PSGꢀandꢀPWMꢀDACꢀclock:ꢀ ꢀ PSGCK
BGRꢀoutputꢀclock:ꢀ ꢀ BGRCK
ꢀ
ꢀ
ꢀ
TheꢀrelationꢀbetweenꢀlockedꢀfrequencyꢀandꢀBRSꢀcanꢀbeꢀ
ꢀ
foundꢀinꢀtheꢀfollowingꢀequation.ꢀ
ꢀ
ꢀ
SPIꢀtransmissionꢀclock:ꢀSPICKꢀ
ꢀ
Equation9ꢁ1ꢀ
FHIGH = CLK32⋅BRS
ꢀ
ꢀ
ꢀ
SYSCK
OSCKꢀandꢀ FHIGH ꢀ areꢀcloseꢀrelated.ꢀValueꢀofꢀ FHIGH ꢀ limitsꢀ
TheꢀsystemꢀclockꢀcanꢀbeꢀswitchedꢀbetweenꢀOSCKꢀandꢀ
CLK32ꢀbyꢀresettingꢀorꢀsettingꢀXSELꢀ(SYS[7]).ꢀAfterꢀXSELꢀisꢀ
setꢀ(orꢀreset),ꢀwarmꢁupꢀcyclesꢀwillꢀbeꢀinitiatedꢀatꢀtheꢀsameꢀ
time.ꢀTheꢀoriginalꢀclockꢀisꢀstillꢀconnectedꢀuntilꢀtheꢀendꢀofꢀ
warmꢁupꢀcycles.ꢀClockꢀbeingꢀusedꢀcanꢀbeꢀreportedꢀbyꢀ
readingꢀXSELꢀback.ꢀ ꢀ
theꢀfrequencyꢀrangeꢀofꢀtheꢀOSCKꢀapplied,ꢀwhichꢀisꢀalsoꢀtheꢀ
lockingꢀrangeꢀofꢀBGR,ꢀandꢀisꢀgivenꢀbyꢀtheꢀfollowingꢀ
equation,ꢀwhereꢀαꢀisꢀtheꢀmodulationꢀstrengthꢀcoefficient.ꢀ
ꢀ
α
OSCK
2
α
α −1
FHIGH
⋅
≤
≤ FHIGH
⋅
ꢀ ꢀ Equation9ꢁ2ꢀ
ꢀ
α
+1
Note:ꢀTestꢀXSELꢀtoꢀconfirmꢀSYSCKꢀisꢀswitchedꢀ
overꢀsuccessfullyꢀbeforeꢀturningꢀdownꢀtheꢀ
originalꢀclock.ꢀ ꢀ
ꢀ
Althoughꢀtheꢀlockedꢀfrequencyꢀisꢀlimitedꢀtoꢀbeꢀaroundꢀ
OSCK,ꢀlowerꢀfrequencyꢀcanꢀstillꢀbeꢀobtainedꢀbyꢀoneꢀ8ꢁbitꢀ
integerꢀdivider,ꢀwhichꢀisꢀassignedꢀbyꢀBDIV.ꢀThusꢀBGRCKꢀ
canꢀbeꢀexpressedꢀbyꢀEquation9ꢁ3.ꢀ
ꢀ
Thereꢀareꢀtwoꢀoptionsꢀforꢀwarmꢁupꢀcycles:ꢀ16ꢀ/ꢀ256ꢀcycles,ꢀ
whichꢀareꢀcontrolledꢀbyꢀWSKPꢀ(SYS[3]).ꢀUsuallyꢀ16ꢀcyclesꢀ
areꢀenoughꢀforꢀOSCꢀandꢀOSCX.ꢀ
ꢀ
FHIGH
BGRCK =
ꢀ
Equation9ꢁ3ꢀ
ꢀ
BDIV
ꢀ
LCDCK
ꢀ
TheꢀLCDꢀcontrollerꢀhasꢀoneꢀfourꢁbitꢀdividerꢀtoꢀgenerateꢀ
LCDCKꢀdirectlyꢀfromꢀOSCKꢀforꢀpixelꢀclockꢀandꢀotherꢀ
operations.ꢀThisꢀdividerꢀisꢀcontrolledꢀbyꢀLCKR[3:0]ꢀandꢀtheꢀ
dataꢀmodeꢀselectionꢀbitꢀLMOD(LCKR[4]).ꢀReferꢀtoꢀTABLEꢀ
11ꢁ3ꢀforꢀsettingsꢀofꢀLCDCK.ꢀ
ꢀ
ꢀ
SPICK
TheꢀSPIꢀblockꢀhasꢀoneꢀthreeꢁbitꢀdividerꢀtoꢀgenerateꢀSPICKꢀ
directlyꢀfromꢀOSCKꢀforꢀtransmissionꢀandꢀotherꢀoperations.ꢀ
ThisꢀdividerꢀisꢀcontrolledꢀbyꢀSCKR[6:4].ꢀReferꢀtoꢀTABLEꢀ
11ꢁ7ꢀforꢀsettingsꢀofꢀSPICK.ꢀ
ꢀ
ꢀ
ꢀ
PSGCK
PSGCKꢀisꢀtheꢀclockꢀusedꢀbyꢀPSGꢀandꢀPWMꢀDAC.ꢀItꢀisꢀ
sourcedꢀfromꢀOSCKꢀtoꢀmakeꢀsureꢀofꢀoneꢀrightꢀandꢀhighꢀ
ꢀ
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Verꢀ2.5ꢀ
21
/75
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9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
