ST2202A
9.1.1 Port-A Interrupt De-bounce
TheꢀST2202ꢀhasꢀaꢀhardwareꢀdeꢁbounceꢀblockꢀforꢀPortꢁAꢀ
interrupt.ꢀItꢀisꢀenabledꢀwithꢀ“1”ꢀandꢀdisableꢀwithꢀ“0”ꢀofꢀPDBN
(PMCR[6]).ꢀTheꢀdeꢁbounceꢀfunctionꢀisꢀactivatedꢀafterꢀfirstꢀ
PortꢁAꢀtransitionꢀisꢀdetected.ꢀItꢀusesꢀOSCXꢀasꢀtheꢀsamplingꢀ
ꢀ
clock.ꢀTheꢀdeꢁbounceꢀtimeꢀisꢀOSCXꢀxꢀ512ꢀcyclesꢀ(aboutꢀ15.6ꢀ
ms).ꢀDataꢀfilteredꢀbyꢀdeꢁbounceꢀpresentsꢀaꢀstableꢀstate,ꢀthenꢀ
theꢀinterruptꢀcanꢀbeꢀissued.ꢀ
TABLE 9-8 Port Miscellaneous Control Register (PMCR)
Address Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
$00F PMCR
R/Wꢀ
PULLꢀ
PDBNꢀ INTEGꢀ CSM1ꢀ CSM0ꢀ
TO2ꢀ
TO1ꢀ
TO0ꢀ
1000ꢀ0000ꢀ
ꢀ
Bitꢀ6:ꢀ ꢀ PDBN :ꢀEnableꢀPortꢁAꢀinterruptꢀdeꢁbounceꢀ
1ꢀ=ꢀDeꢁbounceꢀforꢀPortꢁAꢀinterruptꢀ
0
ꢀ=ꢀNoꢀdeꢁbounceꢀforꢀPortꢁAꢀinterruptꢀ
ꢀ
ꢀ
9.2 External Interrupt
PC0ꢀplaysꢀanotherꢀfunctionꢀofꢀexternalꢀedgeꢁsensitiveꢀinterruptꢀ
source.ꢀFallingꢀorꢀrisingꢀedgeꢀisꢀcontrolledꢀbyꢀINTEG(PMCR[5]).ꢀ
ꢀ
Stepsꢀandꢀprogramꢀexampleꢀareꢀshownꢀbelow.ꢀ
Steps for INTX interrupt operation:
Example:
.
.
1. SetꢀPC0ꢀtoꢀinputꢀmode.ꢀ(PCC[0])
2. SetꢀPF0ꢀtoꢀ“1”
RMB0ꢀ <PCCꢀ
SMB0ꢀ <PFCꢀ
SMB5ꢀ <PMCRꢀ
RMB0ꢀ <IREQꢀ
SMB0ꢀ <IENAꢀ
;ꢀSetꢀinputꢀmode.ꢀ
;ꢀEnableꢀINTXꢀfunctionꢀ
;ꢀRisingꢀedge.ꢀ
;ꢀClearꢀIRQꢀflag.ꢀ
;ꢀEnableꢀINTXꢀinterrupt.ꢀ
3. Selectꢀedgeꢀlevel.ꢀ(INTEG)
4. ClearꢀINTXꢀinterruptꢀrequestꢀflag.ꢀ(IRX)
5. SetꢀINTXꢀinterruptꢀenableꢀbits.ꢀ(IEX)
6. ClearꢀCPUꢀinterruptꢀmaskꢀflagꢀ(I).
ꢀ
CLIꢀ
ꢀ
.
ꢀ
TABLE 9-9 Port Miscellaneous Control Register (PMCR)
Address Name
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
$00F PMCR
R/Wꢀ
PULLꢀ
PDBNꢀ INTEGꢀ CSM1ꢀ CSM0ꢀ
TO2ꢀ
TO1ꢀ
TO0ꢀ
1000ꢀ0000ꢀ
ꢀ
Bitꢀ5:ꢀ ꢀ INTEG :ꢀEdgeꢀoptionsꢀofꢀexternalꢀinterruptꢀ
1ꢀ=ꢀExternalꢀinterruptꢀisꢀrisingꢀedgeꢀtriggeredꢀ
0ꢀ=ꢀExternalꢀinterruptꢀisꢀfallingꢀedgeꢀtriggeredꢀ
ꢀ
ꢀ
Verꢀ2.5ꢀ
18
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75
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9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
