ST2202A
8. INTERRUPT CONTROLLER
TheꢀST2202ꢀsupportsꢀ11ꢀhardwareꢀinternal/externalꢀinterruptsꢀ
asꢀwellꢀasꢀoneꢀsoftwareꢀinterruptꢀBrk.ꢀThereꢀareꢀ12ꢀexceptionꢀ
vectorsꢀforꢀtheseꢀinterruptsꢀandꢀanotherꢀoneꢀforꢀreset.ꢀAllꢀ
ꢀ
Onceꢀanꢀinterruptꢀeventꢀwasꢀenabledꢀandꢀthenꢀhappens,ꢀtheꢀ
CPUꢀwakesꢀupꢀ(ifꢀinꢀeitherꢀwaitꢀmode),ꢀandꢀassociatedꢀbitꢀofꢀ
interruptsꢀareꢀcontrolledꢀbyꢀinterruptꢀdisableꢀflagꢀ“
I
”ꢀ(bit2ꢀofꢀ
interruptꢀrequestꢀregisterꢀ(IREQ)ꢀwillꢀbeꢀset.ꢀIfꢀ“I”ꢀflagꢀisꢀcleared,ꢀ
statusꢀregisterꢀ ),ꢀandꢀinitiateꢀifꢀ“ ”ꢀequalsꢀ“0”.ꢀHardwareꢀ
P
I
theꢀrelatedꢀvectorꢀwillꢀbeꢀfetchedꢀandꢀthenꢀtheꢀinterruptꢀserviceꢀ
routineꢀ(ISR)ꢀwillꢀbeꢀexecuted.ꢀInterruptꢀrequestꢀflagꢀcanꢀbeꢀ
clearedꢀbyꢀtwoꢀmethods.ꢀOneꢀisꢀtoꢀwriteꢀ“0”ꢀtoꢀIREQ,ꢀtheꢀotherꢀ
isꢀtoꢀinitiateꢀrelatedꢀinterruptꢀserviceꢀroutine.ꢀHardwareꢀwillꢀ
automaticallyꢀclearꢀtheꢀInterruptꢀrequestꢀflag.ꢀAllꢀinterruptꢀ
vectorsꢀareꢀlistedꢀinꢀTABLEꢀ8ꢁ1.
interruptsꢀareꢀfurtherꢀcontrolledꢀbyꢀinterruptꢀenableꢀregisterꢀ
IENA.ꢀSettingꢀbitsꢀofꢀIENAꢀenablesꢀrespectiveꢀinterrupts.ꢀ ꢀ
ꢀ
Theꢀinterruptꢀcontrollerꢀownsꢀoneꢀpriorityꢀarbitrator.ꢀWhenꢀmoreꢀ
thanꢀoneꢀinterruptsꢀhappenꢀatꢀtheꢀsameꢀtime,ꢀtheꢀoneꢀwithꢀ
lowerꢀpriorityꢀnumberꢀwillꢀbeꢀexecutedꢀfirst.ꢀReferꢀtoꢀTABLEꢀ8ꢁ1ꢀ
forꢀprioritiesꢀofꢀinterrupts.ꢀ
ꢀ
TABLE 8-1 Interrupt Vectors
Vector Address Priority
Name
BRKꢀ
RESETꢀ
ꢁꢀ
Signal Source
Internalꢀ
Description
SoftwareꢀBRKꢀoperationꢀvectorꢀ
Resetꢀvectorꢀ
$7FFF,$7FFEꢀ
$7FFD,$7FFCꢀ
$7FFB,$7FFAꢀ
$7FF9,$7FF8ꢀ
$7FF7,$7FF6ꢀ
$7FF5,$7FF4ꢀ
$7FF3,$7FF2ꢀ
$7FF1,$7FF0ꢀ
$7FEF,$7FEEꢀ
$7FED,$7FECꢀ
$7FEB,$7FEAꢀ
$7FE9,$7FE8ꢀ
$7FE7,$7FE6ꢀ
$7FE5,$7FE4ꢀ
$7FE3,$7FE2ꢀ
1ꢀ
0ꢀ
Externalꢀ
ꢁꢀ
ꢁꢀ
Reservedꢀ
INTXꢀ
DACꢀ
T0ꢀ
Externalꢀ
Internalꢀ
6ꢀ
PC0ꢀedgeꢀinterruptꢀ
7ꢀ
ReloadꢀDACꢀdataꢀinterruptꢀ
Timer0ꢀinterruptꢀ
Internal/Externalꢀ
Internal/Externalꢀ
Externalꢀ
Internalꢀ
8ꢀ
T1ꢀ
9ꢀ
Timer1ꢀinterruptꢀ
PTꢀ
10ꢀ
11ꢀ
12ꢀ
ꢁꢀ
PortꢁAꢀtransitionꢀinterruptꢀ
BaseꢀTimerꢀinterruptꢀ
LCDꢀFrameꢀinterruptꢀ
Reservedꢀ
BTꢀ
LCDꢀ
ꢁꢀ
Internalꢀ
ꢁꢀ
STXꢀ
SRXꢀ
UTXꢀ
URXꢀ
Externalꢀ
Externalꢀ
Externalꢀ
Externalꢀ
2ꢀ
SPIꢀtransmitꢀbufferꢀemptyꢀinterruptꢀ
SPIꢀreceiveꢀbufferꢀreadyꢀinterruptꢀ
UARTꢀreceiverꢀinterruptꢀ
UARTꢀtransmitterꢀinterruptꢀ
3ꢀ
4ꢀ
5ꢀ
ꢀ
TABLE 8-2 Interrupt Request Register (IREQ)
Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8
Address Name
R/W
Default
$03C IREQL
$03D IREQH
R/Wꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
IRLCDꢀ
ꢁꢀ
IRBTꢀ
ꢁꢀ
IRPTꢀ
ꢁꢀ
IRT1ꢀ
IRT0ꢀ
IRDACꢀ
IRXꢀ
ꢁ000ꢀ0000ꢀ
IRURXꢀ IRUTXꢀ IRSRXꢀ IRSTXꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
ꢀ
Bitꢀ1:ꢀ ꢀ IRDAC:ꢀDACꢀreloadꢀinterruptꢀrequestꢀbitꢀ
Bitꢀ0:ꢀ ꢀ IRX:ꢀINTXꢀinterruptꢀrequestꢀbitꢀ
1ꢀ=ꢀDACꢀtimeꢀoutꢀinterruptꢀoccursꢀ
1ꢀ=ꢀINTXꢀedgeꢀinterruptꢀoccursꢀ
0
ꢀ=ꢀDACꢀtimeꢀoutꢀinterruptꢀdoesn’tꢀoccurꢀ
0ꢀ=ꢀINTXꢀedgeꢀinterruptꢀdoesn’tꢀoccurꢀ
Bitꢀ2:ꢀ ꢀ IRT0:ꢀTimer0ꢀinterruptꢀrequestꢀbitꢀ
Bitꢀ3:ꢀ ꢀ IRT1:ꢀTimer1ꢀinterruptꢀrequestꢀbitꢀ
1ꢀ=ꢀTimer0ꢀoverflowꢀinterruptꢀoccursꢀ
1ꢀ=ꢀTimer1ꢀoverflowꢀinterruptꢀoccursꢀ
0ꢀ=ꢀTimer0ꢀoverflowꢀinterruptꢀdoesn’tꢀoccurꢀ
0ꢀ=ꢀTimer1ꢀoverflowꢀinterruptꢀdoesn’tꢀoccurꢀ
Bitꢀ4:ꢀ ꢀ IRPT:ꢀPortꢁAꢀinterruptꢀrequestꢀbitꢀ
Bitꢀ5:ꢀ ꢀ IRBT:ꢀBaseꢀTimerꢀinterruptꢀrequestꢀbitꢀ
1ꢀ=ꢀPortꢁAꢀtransitionꢀinterruptꢀoccursꢀ
1ꢀ=ꢀTimeꢀbaseꢀinterruptꢀoccursꢀ
0ꢀ=ꢀTimeꢀbaseꢀinterruptꢀdoesn’tꢀoccurꢀ
0ꢀ=ꢀPortꢁAꢀtransitionꢀinterruptꢀdoesn’tꢀoccurꢀ
Bitꢀ6:ꢀ ꢀ IRLCD:ꢀLCDꢀframeꢀInterruptꢀrequestꢀbitꢀ
Bitꢀ8:ꢀ ꢀ IRSTX:ꢀSPIꢀtransmitterꢀinterruptꢀrequestꢀbitꢀ
1ꢀ=ꢀLCDꢀFrameꢀinterruptꢀoccursꢀ
1ꢀ=ꢀSPIꢀtransmitꢀbufferꢀisꢀemptyꢀ
0ꢀ=ꢀLCDꢀFrameꢀinterruptꢀdoesn’tꢀoccurꢀ
0ꢀ=ꢀSPIꢀtransmitꢀbufferꢀisꢀoccupiedꢀ
Bitꢀ9:ꢀ ꢀ IRSRX:ꢀSPIꢀreceiverꢀinterruptꢀrequestꢀbitꢀ
Bitꢀ10:ꢀ ꢀ IRUTX:ꢀUARTꢀtransmitterꢀinterruptꢀrequestꢀbitꢀ
1ꢀ=ꢀSPIꢀreceiveꢀbufferꢀisꢀreadyꢀ
1ꢀ=ꢀUARTꢀdataꢀtransmissionꢀcompletesꢀ
0ꢀ=ꢀSPIꢀreceiveꢀbufferꢀisꢀnotꢀreadyꢀ
0ꢀ=ꢀUARTꢀdataꢀtransmissionꢀnotꢀcompletesꢀ
Verꢀ2.5ꢀ
12
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
