ST2202A
7. MEMORY CONFIGURATION
7.1 Memory map
TheꢀlogicalꢀmemoryꢀspaceꢀofꢀST2202ꢀisꢀdividedꢀintoꢀ3ꢀparts:ꢀ
$0000~$0FFFꢀ(4K),ꢀ$4000~$7FFFꢀ(16K),ꢀandꢀ$8000~FFFFꢀ
(32K).ꢀFirstꢀisꢀforꢀcontrolꢀregisters,ꢀstackꢀandꢀsystemꢀmemory.ꢀ
Secondꢀandꢀthirdꢀareꢀbankedꢀareas.ꢀLogicalꢀaddressꢀinꢀtheseꢀ
Bothꢀcanꢀreferꢀtoꢀaꢀmaximumꢀspaceꢀofꢀ64Mꢀbytes.ꢀ
ꢀ
Onlyꢀ44Mꢀ(28MꢀwhenꢀCSM0=”0”)ꢀbytesꢀisꢀ
addressableꢀbyꢀchipꢀselects.ꢀ
ꢀ
twoꢀareasꢀcombinesꢀtwoꢀbankꢀregisters,ꢀPRRꢀandꢀDRR
ꢀ
respectively,ꢀandꢀthenꢀbeꢀmappedꢀtoꢀaꢀphysicalꢀaddress.ꢀPRR
ꢀ
ReferꢀtoꢀFIGUREꢀ7ꢁ1ꢀforꢀmemoryꢀmappingꢀofꢀST2202.ꢀ
isꢀtheꢀProgramꢀROMꢀBankꢀRegisterꢀandꢀisꢀ12ꢁbitꢀlong,ꢀwhileꢀ
DRRꢀisꢀtheꢀDataꢀROMꢀBankꢀRegisterꢀofꢀtheꢀlengthꢀofꢀ11ꢀbits.ꢀ
ꢀ
ꢀ
0000
0000000~
PRRꢀ=ꢀ001H
0003FFF
ControlꢀRegister
007F
0080
DRRꢀ=ꢀ000H
0004000~
PRRꢀ=ꢀ000H
0007FFF
ZeroꢀPageꢀ
UserꢀMemory
00FF
0008000~
PRRꢀ=ꢀ003H
000BFFF
0100
Stack
01FF
DRRꢀ=ꢀ001H
000C000~
PRRꢀ=ꢀ002H
000FFFF
0200
UserꢀMemoryꢀ/ꢀ
DisplayꢀMemory
0FFF
1000
Reserved
3FFF
4000
ProgramꢀMemory
(PRR)
16Kꢀbytes
7FE2
7FFF
8000
InterruptꢀVector
DataꢀMemory
(DRR)
32Kꢀbytes
3FF0000~
PRRꢀ=ꢀFFDH
3FF3FFF
DRRꢀ=ꢀ7FEH
3FF4000~
PRRꢀ=ꢀFFCH
3FF7FFF
3FF8000~
PRRꢀ=ꢀFFFH
3FFBFFF
DRRꢀ=ꢀ7FFH
3FFC000~
PRRꢀ=ꢀFFEH
3FFFFFF
FFFF
PhysicalꢀMemoryꢀMapping
64MꢀBytes
CPUꢀMemoryꢀMapping
.
ꢀ
FIGURE 7-1 Memory Mapping
Verꢀ2.5ꢀ
8/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
