ST2202A
7. MEMORY CONFIGURATION
7.1 Memory map
The logical memory space of ST2202 is divided into 3 parts:
$0000~$0FFF (4K), $4000~$7FFF (16K), and $8000~FFFF
(32K). First is for control registers, stack and system memory.
Second and third are banked areas. Logical address in these
two areas combines two bank registers,
PRR
and
DRR
respectively, and then be mapped to a physical address.
PRR
is the Program ROM Bank Register and is 12-bit long, while
DRR
is the Data ROM Bank Register of the length of 11 bits.
Both can refer to a maximum space of 64M bytes.
Only 44M (28M when
CSM0
=”0”) bytes is
addressable by chip selects.
Refer to FIGURE 7-1 for memory mapping of ST2202.
0000
007F
0080
00FF
0100
01FF
0200
0FFF
1000
Reserved
3FFF
4000
User Memory /
Display Memory
Control Register
Zero Page
User Memory
Stack
0000000~
0003FFF
0004000~
0007FFF
0008000~
000BFFF
000C000~
000FFFF
PRR = 001H
DRR = 000H
PRR = 000H
PRR = 003H
DRR = 001H
PRR = 002H
Program Memory
(PRR)
16K bytes
7FE2
7FFF
8000
Interrupt Vector
Data Memory
(DRR)
32K bytes
3FF0000~
3FF3FFF
3FF4000~
3FF7FFF
3FF8000~
3FFBFFF
3FFC000~
3FFFFFF
PRR = FFDH
DRR = 7FEH
PRR = FFCH
PRR = FFFH
DRR = 7FFH
PRR = FFEH
FFFF
CPU Memory Mapping
.
Physical Memory Mapping
64M Bytes
FIGURE 7-1 Memory Mapping
Ver 2.5
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9/16/2008
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
