ST2202A
ꢀ
$040
$041
$042
$043
$044
$045
$047
$048
$049
$04A
LSSAL*
LSSAH*
LVPW*
LXMAX
LYMAX
LPAN
Wꢀ
Wꢀ
Wꢀ
R/Wꢀ
R/Wꢀ
R/Wꢀ
R/Wꢀ
Wꢀ
SSA[7]ꢀ
SSA[15]ꢀ
VP[7]ꢀ
XM[7]ꢀ
YM[7]ꢀ
ꢁꢀ
LPWRꢀ
ꢁꢀ
ꢁꢀ
SSA[6]ꢀ
SSA[14]ꢀ
VP[6]ꢀ
XM[6]ꢀ
YM[6]ꢀ
ꢁꢀ
BLNKꢀ
ꢁꢀ
ꢁꢀ
SSA[5]ꢀ
SSA[13]ꢀ
VP[5]ꢀ
XM[5]ꢀ
YM[5]ꢀ
ꢁꢀ
REVꢀ
ꢁꢀ
FRA[5]ꢀ
ꢁꢀ
SSA[4]ꢀ
SSA[12]ꢀ
VP[4]ꢀ
XM[4]ꢀ
YM[4]ꢀ
ꢁꢀ
SSA[3]ꢀ
SSA[11]ꢀ
VP[3]ꢀ
XM[3]ꢀ
YM[3]ꢀ
ꢁꢀ
SSA[2]ꢀ
SSA[10]ꢀ
VP[2]ꢀ
XM[2]ꢀ
YM[2]ꢀ
PAN[2]ꢀ
ꢁꢀ
LCK[2]ꢀ
FRA[2]ꢀ
AC[2]ꢀ
SSA[1]ꢀ
SSA[9]ꢀ
VP[1]ꢀ
XM[1]ꢀ
YM[1]ꢀ
PAN[1]ꢀ
ꢁꢀ
LCK[1]ꢀ
FRA[1]ꢀ
AC[1]ꢀ
SSA[0]ꢀ 0000ꢀ0000ꢀ
SSA[8]ꢀ 0000ꢀ0000ꢀ
VP[0]ꢀ
XM[0]ꢀ
YM[0]ꢀ
PAN[0]ꢀ
ꢁꢀ
0000ꢀ0000ꢀ
0000ꢀ0000ꢀ
0000ꢀ0000ꢀ
ꢁꢀꢁꢀꢁꢀꢁꢀꢁ000ꢀ
100ꢁꢀꢁꢀꢁꢀꢁꢀꢁꢀ
LCTR
ꢁꢀ
ꢁꢀ
LCKR*
LFRA*
LAC
LMODꢀ
FRA[4]ꢀ
AC[4]ꢀ
LCK[3]ꢀ
FRA[3]ꢀ
AC[3]ꢀ
LCK[0]ꢀ ꢁꢀꢁꢀꢁ0ꢀ0000ꢀ
FRA[0]ꢀ ꢁꢀꢁꢀ00ꢀ0000ꢀ
Wꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
AC[0]ꢀ
ꢁꢀꢁꢀꢁ0ꢀ0000ꢀ
$04B
$04C
$04E
$050
$051
$052
$053
LPWM
PL*
PCL*
SDAT0AL
SDATAH
SCTR
R/Wꢀ
R/Wꢀ
Wꢀ
R/Wꢀ
R/Wꢀ
R/Wꢀ
R/Wꢀ
Rꢀ
ꢁꢀ
ꢁꢀ
LPWM[5]ꢀ LPWM[4]ꢀ LPWM[3]ꢀ LPWM[2]ꢀ LPWM[1]ꢀ LPWM[0]ꢀ ꢁꢀꢁꢀ00ꢀ0000ꢀ
PL[7]ꢀ
PCL[7]ꢀ
SD[7]ꢀ
SD[15]ꢀ
SPIENꢀ
ꢁꢀ
PL[6]ꢀ
PCL[6]ꢀ
SD[6]ꢀ
SD[14]ꢀ
RXIENꢀ
SCK[2]ꢀ
RXRDYꢀ
PL[5]ꢀ
PCL[5]ꢀ
SD[5]ꢀ
SD[13]ꢀ
ERIENꢀ
SCK[1]ꢀ
TXEMPꢀ
PL[4]ꢀ
PCL[4]ꢀ
SD[4]ꢀ
SD[12]ꢀ
MERENꢀ
SCK[0]ꢀ
SBZꢀ
PL[3]ꢀ
PCL[3]ꢀ
SD[3]ꢀ
SD[11]ꢀ
DRINVꢀ
BC[3]ꢀ
ꢁꢀ
PL[2]ꢀ
PCL[2]ꢀ
SD[2]ꢀ
SD[10]ꢀ
POLꢀ
PL[1]ꢀ
PCL[1]ꢀ
SD[1]ꢀ
SD[9]ꢀ
PHAꢀ
PL[0]ꢀ
PCL[0]ꢀ 0000ꢀ0000ꢀ
SD[0]ꢀ
SD[8]ꢀ
SMODꢀ 0000ꢀ0000ꢀ
BC[0]ꢀ ꢁ000ꢀ0000ꢀ
1111ꢀ1111ꢀ
????ꢀ????ꢀ
????ꢀ????ꢀ
SCKR
BC[2]ꢀ
MDERRꢀ
BC[1]ꢀ
OERRꢀ
ꢁꢀ
BCERRꢀ ꢁ000ꢀꢁ000ꢀ
ꢀ
$054
SSR*
Wꢀ
WriteꢀanyꢀvalueꢀtoꢀclearꢀSSRꢀ
$060
$061
UCTR
R/Wꢀ
Rꢀ
Wꢀ
R/Wꢀ
R/Wꢀ
R/Wꢀ
R/Wꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
FERꢀ
ꢁꢀ
TXINVꢀ
ꢁꢀ
UD[6]ꢀ
BRS[6]ꢀ
BDIV[6]ꢀ
ꢁꢀ
PERꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
UD[5]ꢀ
BRS[5]ꢀ
BDIV[5]ꢀ
ꢁꢀ
OERꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
UD[4]ꢀ
BRS[4]ꢀ
BDIV[4]ꢀ
PENꢀ
RXBZꢀ
RXTRGꢀ
ꢁꢀ
PMODꢀ
RXENꢀ
RXENꢀ
PW1ꢀ
BSTRꢀ
UD[2]ꢀ
UMODꢀ
TXBZꢀ
TXTRGꢀ
PW0ꢀ
BMODꢀ
UD[1]ꢀ
BRS[1]ꢀ
BDIV[1]ꢀ
BRKꢀ
TXENꢀ
TXENꢀ
IRENꢀ
BGRENꢀ 0ꢁꢀꢁꢀꢁꢀꢁ000ꢀ
UD[0]ꢀ ????ꢀ????ꢀ
ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
ꢁ000ꢀ0000ꢀ
ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
00ꢁꢀꢁꢀꢁ000ꢀ
USTR*
$062
$063
$064
$066
$067
IRCTR
BCTR
UDATA
BRS
RXINVꢀ
TESTꢀ
UD[7]ꢀ
BRS[7]ꢀ
BDIV[7]ꢀ
ꢁꢀ
UD[3]ꢀ
BRS[3]ꢀ
BDIV[3]ꢀ
BRS[2]ꢀ
BDIV[2]ꢀ
BRS[0]ꢀ ????ꢀ????ꢀ
BDIV[0]ꢀ ????ꢀ????ꢀ
BDIV
Note:ꢀ ꢀ1.ꢀUndefinedꢀbytesꢀandꢀbitsꢀshouldꢀnotꢀbeꢀused,ꢀpleaseꢀkeepꢀitꢀ“0”.ꢀ
Do not use read-modify-write instructions, RMBx and SMBx, to write-only registers.
*
ꢀ
7.3 Bank Registers
zeroꢀandꢀbit[7:0]ꢀwillꢀbeꢀreplacedꢀbyꢀIRR.ꢀThisꢀreplacementꢀ
lastsꢀuntilꢀinstructionꢀRTIꢀisꢀmet.ꢀThatꢀis,ꢀtheꢀinterruptꢀvectorsꢀ
andꢀserviceꢀroutinesꢀwillꢀallꢀbaseꢀonꢀIRR.ꢀOperationꢀofꢀIRRꢀisꢀ
alsoꢀenabledꢀbyꢀIRRENꢀofꢀSYS.ꢀ ꢀ
Thereꢀareꢀfourꢀkindsꢀofꢀbankꢀregisters,ꢀinterruptꢀbankꢀregisterꢀ
(IRR),ꢀprogramꢀROMꢀbankꢀregisterꢀ(PRR),ꢀdataꢀROMꢀbankꢀ
registerꢀ(DRR),ꢀandꢀDMAꢀsourceꢀdataꢀbankꢀregisterꢀ(DMR).ꢀ
IRR,ꢀPRRꢀreferꢀtoꢀlogicꢀaddressꢀrangeꢀofꢀ$4000~$7FFF,ꢀwhileꢀ
DRR,ꢀDMRꢀreferꢀtoꢀtheꢀrangeꢀofꢀ$8000~$FFFF.ꢀTheꢀregisterꢀ
length,ꢀaddressableꢀrange,ꢀandꢀsizeꢀareꢀlistedꢀinꢀTABLEꢀ7ꢁ2.ꢀ
Whenꢀnormalꢀprocessꢀisꢀrunning,ꢀaddressꢀfallsꢀinꢀoneꢀofꢀtheꢀ
twoꢀareasꢀwillꢀactivateꢀeitherꢀPRRꢀorꢀDRR.ꢀ
ꢀ
ꢀ
Althoughꢀaꢀmaximumꢀnumberꢀofꢀ64Mꢀbytesꢀcanꢀbeꢀaddressed,ꢀ
theꢀphysicalꢀsizeꢀisꢀlowerꢀthanꢀthatꢀbecauseꢀofꢀtheꢀlimitꢀofꢀchipꢀ
selects.ꢀPleaseꢀreferꢀtoꢀsectionꢀ10ꢀforꢀmoreꢀdetails.ꢀ
Inꢀtheꢀcaseꢀofꢀinterrupts,ꢀbit[11:8]ꢀofꢀPRRꢀwillꢀbeꢀmaskedꢀtoꢀ
ꢀ
TABLE 7-2 Bank Registers and Addressable Range
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Addressabl
e Range
Address Name R/W Bit 7
Bit 0
Size
$0000000~ꢀ
$03FFFFFꢀ
$031
IRR
R/Wꢀ IRR[7]ꢀ IRR[6]ꢀ IRR[5]ꢀ IRR[4]ꢀ IRR[3]ꢀ IRR[2]ꢀ IRR[1]ꢀ IRR[0]ꢀ
4Mꢀ
$032
$033
$034
$035
$036
$037
PRRL
PRRH
DRRL
DRRH
DMRL
DMRH
R/Wꢀ PRR[7]ꢀ PRR[6]ꢀ PRR[5]ꢀ PRR[4]ꢀ PRR[3]ꢀ PRR[2]ꢀ PRR[1]ꢀ PRR[0]ꢀ $0000000~ꢀ
$3FFFFFFꢀ
64M*ꢀ
64M*ꢀ
64M*ꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
PRR[11]ꢀ PRR[10]ꢀ PRR[9]ꢀ PRR[8]ꢀ
R/Wꢀ DRR[7]ꢀ DRR[6]ꢀ DRR[5]ꢀ DRR[4]ꢀ DRR[3]ꢀ DRR[2]ꢀ DRR[1]ꢀ DRR[0]ꢀ $0000000~ꢀ
$3FFFFFFꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
DRR[10]ꢀ DRR[9]ꢀ DRR[8]ꢀ
R/Wꢀ DMR[7]ꢀ DMR[6]ꢀ DMR[5]ꢀ DMR[4]ꢀ DMR[3]ꢀ DMR[2]ꢀ DMR[1]ꢀ DMR[0]ꢀ $0000000~ꢀ
$3FFFFFFꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
ꢁꢀ
DMR[10]ꢀ DMR[9]ꢀ DMR[8]ꢀ
Note:ꢀ*ꢀPleaseꢀreferꢀtoꢀsectionꢀ10ꢀforꢀtheꢀlimitꢀofꢀaddressableꢀsize.ꢀ
ꢀ
TABLE 7-3 System Control Register SYS
Address Name
Bit 7
XSELꢀ
XSELꢀ
Bit 6
OSTPꢀ
OSTPꢀ
Bit 5
XSTPꢀ
XSTPꢀ
Bit 4
Bit 3
WSKPꢀ WAITꢀ IRRENꢀ HIGHꢀ
WSKPꢀ WAITꢀ IRRENꢀ LVDENꢀ 0000ꢀ0000ꢀ
Bit 2
Bit 1
Bit 0
Default
0000ꢀ0001ꢀ
Rꢀ
Wꢀ
$030 SYS
ꢁꢀ
ꢀ
Bitꢀ1:ꢀ ꢀ IRRENꢀ:ꢀEnable/DisableꢀBankꢀregisterꢀIRRꢀ
ꢀ=ꢀDisableꢀIRRꢀ
1ꢀ=ꢀEnableꢀIRRꢀ
0
Verꢀ2.5ꢀ
10
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
