ST2202A
Bitꢀ11:ꢀ ꢀ IRURX:ꢀUARTꢀreceiverꢀinterruptꢀrequestꢀbitꢀ
ꢀ
ꢀ
1ꢀ=ꢀUARTꢀdataꢀreceivingꢀcompletesꢀ
0ꢀ=ꢀUARTꢀdataꢀreceivingꢀnotꢀcompletesꢀ
ꢀ
TABLE 8-3 Interrupt Enable Register (IENA)
Address Name
R/W
Bit 7/15 Bit 6/14 Bit 5/13 Bit 4/12 Bit 3/11 Bit 2/10 Bit 1/9 Bit 0/8
Default
ꢁꢀ000ꢀ0000ꢀ
$03E IENAL
$03F IENAH
R/Wꢀ
R/Wꢀ
ꢁꢀ
ꢁꢀ
IELCDꢀ
ꢁꢀ
IEBTꢀ
ꢁꢀ
IEPTꢀ
ꢁꢀ
IET1ꢀ
IET0ꢀ
IEDACꢀ
IEXꢀ
IEURXꢀ IEUTXꢀ IESRXꢀ IESTXꢀ ꢁꢀꢁꢀꢁꢀꢁꢀ0000ꢀ
ꢀ
Bitx:ꢀ ꢀ 1ꢀ=ꢀEnableꢀrespectiveꢀinterruptꢀ
0ꢀ=ꢀDisableꢀrespectiveꢀinterruptꢀ
ꢀ
ꢀ
8.1 Interrupt Description
interruptꢀmaskꢀflagꢀ(I).ꢀProgramꢀcounterꢀwillꢀbeꢀloadedꢀwithꢀtheꢀ
T1ꢀvectorꢀfromꢀlocationsꢀ$7FF2ꢀandꢀ$7FF3.ꢀ
ꢀ
Brk
Instructionꢀ‘BRK’ꢀwillꢀcauseꢀsoftwareꢀinterruptꢀwhenꢀinterruptꢀ
disableꢀflagꢀ( )ꢀisꢀcleared.ꢀHardwareꢀwillꢀpushꢀ‘PC’,ꢀ‘ ꢀ’ꢀregistersꢀ
toꢀstackꢀandꢀthenꢀsetsꢀinterruptꢀdisableꢀflagꢀ( ).ꢀProgramꢀ
I
P
ꢀ
PT Interrupt
I
counterꢀwillꢀbeꢀloadedꢀwithꢀtheꢀBRKꢀvectorꢀfromꢀlocationsꢀ
$7FFEꢀandꢀ$7FFF.ꢀ
TheꢀIRPTꢀ(PortꢁAꢀinterruptꢀrequest)ꢀflagꢀwillꢀbeꢀsetꢀwhileꢀPortꢁAꢀ
transitionꢀsignalꢀoccurs.ꢀWithꢀIEPTꢀ(PTꢀinterruptꢀenable)ꢀbeingꢀ
set,ꢀtheꢀPTꢀinterruptꢀwillꢀbeꢀexecute,ꢀandꢀinterruptꢀmaskꢀflagꢀwillꢀ
beꢀcleared.ꢀHardwareꢀwillꢀpushꢀ‘PC’,ꢀ ꢀ ‘Pꢀ’ꢀRegisterꢀtoꢀstackꢀandꢀ
setꢀinterruptꢀmaskꢀflagꢀ(I).ꢀProgramꢀcounterꢀwillꢀbeꢀloadedꢀwithꢀ
theꢀPTꢀvectorꢀfromꢀlocationsꢀ$7FF0ꢀandꢀ$7FF1.
ꢀ
Reset
Aꢀpositiveꢀtransitionꢀofꢀ RESET ꢀ pinꢀwillꢀmakeꢀanꢀinitializationꢀ
sequenceꢀtoꢀbegin.ꢀAfterꢀtheꢀsystemꢀhasꢀbeenꢀoperating,ꢀoneꢀ
lowꢀlevelꢀsignalꢀonꢀthisꢀlineꢀofꢀatꢀleastꢀtwoꢀclockꢀcyclesꢀwillꢀ
ceaseꢀST2202ꢀactivity.ꢀWhenꢀaꢀpositiveꢀedgeꢀisꢀdetected,ꢀthereꢀ
isꢀanꢀinitializationꢀsequenceꢀlastingꢀsixꢀclockꢀcycles.ꢀThenꢀtheꢀ
interruptꢀdisableꢀflagꢀisꢀset,ꢀtheꢀdecimalꢀmodeꢀisꢀclearedꢀandꢀ
theꢀprogramꢀcounterꢀwillꢀbeꢀloadedꢀwithꢀtheꢀresetꢀvectorꢀfromꢀ
locationsꢀ$7FFCꢀ(lowꢀbyte)ꢀandꢀ$7FFDꢀ(highꢀbyte).ꢀThisꢀisꢀtheꢀ
startꢀlocationꢀforꢀprogramꢀflow.ꢀThisꢀinputꢀshouldꢀbeꢀhighꢀinꢀ
normalꢀoperation.ꢀ
ꢀ
BT Interrupt
TheꢀIRBTꢀ(Baseꢀtimerꢀinterruptꢀrequest)ꢀflagꢀwillꢀbeꢀsetꢀwhenꢀ
BaseꢀTimerꢀoverflows.ꢀTheꢀBTꢀinterruptꢀwillꢀbeꢀexecutedꢀonceꢀ
theꢀIEBTꢀ(BTꢀinterruptꢀenable)ꢀisꢀsetꢀandꢀtheꢀinterruptꢀmaskꢀflagꢀ
isꢀcleared.ꢀHardwareꢀwillꢀpushꢀ‘PC’,ꢀ ꢀ ‘Pꢀ’ꢀRegisterꢀtoꢀstackꢀandꢀ
setꢀinterruptꢀmaskꢀflagꢀ(I).ꢀProgramꢀcounterꢀwillꢀbeꢀloadedꢀwithꢀ
theꢀBTꢀvectorꢀfromꢀlocationsꢀ$7FEEꢀandꢀ$7FEF.
ꢀ
LCD Frame Interrupt
ꢀ
INTX Interrupt
TheꢀIRLCDꢀ(LCDꢀframeꢀinterruptꢀrequest)ꢀflagꢀwillꢀbeꢀsetꢀwhenꢀ
oneꢀnewꢀdisplayꢀframeꢀcycleꢀstarts.ꢀThisꢀinterruptꢀisꢀveryꢀusefulꢀ
forꢀsoftwareꢀgrayscaleꢀdesign.ꢀTheꢀLCDꢀframeꢀinterruptꢀwillꢀbeꢀ
executedꢀonceꢀtheꢀIELCDꢀ(LCDꢀframeꢀinterruptꢀenable)ꢀisꢀsetꢀ
andꢀtheꢀinterruptꢀmaskꢀflagꢀisꢀcleared.ꢀHardwareꢀwillꢀpushꢀPC
andꢀ ꢀregistersꢀtoꢀstackꢀandꢀsetꢀinterruptꢀdisableꢀflagꢀ“ ”.ꢀ
TheꢀIRXꢀ(INTXꢀinterruptꢀrequest)ꢀflagꢀwillꢀbeꢀsetꢀwhileꢀINTXꢀ
edgeꢀsignalꢀoccurs.ꢀTheꢀINTXꢀinterruptꢀwillꢀbeꢀactiveꢀwhenꢀIEXꢀ
(INTXꢀinterruptꢀenable)ꢀisꢀset,ꢀandꢀinterruptꢀdisableꢀflagꢀisꢀ
cleared.ꢀHardwareꢀwillꢀpushꢀ‘PC’,ꢀ‘Pꢀ’ꢀregistersꢀtoꢀstackꢀandꢀ
setsꢀinterruptꢀdisableꢀflagꢀ(
withꢀtheꢀINTXꢀvectorꢀfromꢀlocationsꢀ$7FF8ꢀandꢀ$7FF9.ꢀ
ꢀ
I).ꢀProgramꢀcounterꢀwillꢀbeꢀloadedꢀ
P
I
ProgramꢀcounterꢀPCꢀwillꢀbeꢀloadedꢀwithꢀtheꢀLCDꢀvectorꢀfromꢀ
locationsꢀ$7FECꢀandꢀ$7FED.ꢀ
ꢀ
DAC Interrupt
TheꢀIRDACꢀ(DACꢀinterruptꢀrequest)ꢀflagꢀwillꢀbeꢀsetꢀwhileꢀreloadꢀ
signalꢀofꢀDACꢀoccurs.ꢀThenꢀtheꢀDACꢀinterruptꢀwillꢀbeꢀexecutedꢀ
ifꢀIEDACꢀ(DACꢀinterruptꢀenable)ꢀisꢀset,ꢀandꢀinterruptꢀdisableꢀ
flagꢀisꢀcleared.ꢀHardwareꢀwillꢀpushꢀ‘PC’,ꢀ ꢀ ‘Pꢀ’ꢀRegisterꢀtoꢀstackꢀ
andꢀsetꢀinterruptꢀmaskꢀflagꢀ(I).ꢀProgramꢀcounterꢀwillꢀbeꢀloadedꢀ
withꢀtheꢀDACꢀvectorꢀfromꢀlocationsꢀ$7FF6ꢀandꢀ$7FF7.ꢀ
ꢀ
ꢀ
SPI Interrupt
ThereꢀareꢀtwoꢀinterruptsꢀforꢀSPIꢀtransmitterꢀandꢀreceiverꢀ
respectively.ꢀIRSTXꢀ(SPIꢀtransmitterꢀinterruptꢀrequest)ꢀflagꢀwillꢀ
beꢀsetꢀwhenꢀSPIꢀtransmitꢀbufferꢀisꢀempty.ꢀIRSRXꢀ(SPIꢀreceiverꢀ
interruptꢀrequest)ꢀflagꢀwillꢀbeꢀsetꢀwhenꢀSPIꢀcompletesꢀoneꢀ
receivingꢀdataꢀandꢀtheꢀreceiveꢀbufferꢀisꢀready.ꢀTheꢀSPIꢀ
interruptsꢀwillꢀbeꢀexecutedꢀonceꢀtheꢀrelatedꢀenableꢀflagꢀIESRX,ꢀ
IESTXꢀareꢀsetꢀandꢀtheꢀinterruptꢀdisableꢀflagꢀ“
Hardwareꢀwillꢀpushꢀ‘PC’,ꢀ‘ ꢀ’ꢀregistersꢀtoꢀstackꢀandꢀsetꢀ“
ProgramꢀcounterꢀwillꢀbeꢀloadedꢀwithꢀtheꢀSPIꢀvectorꢀfromꢀ
locationsꢀ$7FE7,ꢀ$7FE6,ꢀandꢀ$7FE9,ꢀ$7FE8.
ꢀ
T0 Interrupt
I
”ꢀisꢀcleared.ꢀ
TheꢀIRT0ꢀ(TIMER0ꢀinterruptꢀrequest)ꢀflagꢀwillꢀbeꢀsetꢀwhileꢀ
Timer0ꢀoverflows.ꢀWithꢀIET0ꢀ(TIMER0ꢀinterruptꢀenable)ꢀbeingꢀ
set,ꢀtheꢀT0ꢀinterruptꢀwillꢀexecute,ꢀandꢀinterruptꢀmaskꢀflagꢀwillꢀbeꢀ
cleared.ꢀHardwareꢀwillꢀpushꢀ‘PC’,ꢀ ꢀ ‘Pꢀ’ꢀRegisterꢀtoꢀstackꢀandꢀ
setꢀinterruptꢀmaskꢀflagꢀ(I).ꢀProgramꢀcounterꢀwillꢀbeꢀloadedꢀwithꢀ
theꢀT0ꢀvectorꢀfromꢀlocationsꢀ$7FF4ꢀandꢀ$7FF5.ꢀ
ꢀ
P
I”ꢀflag.ꢀ
ꢀ
UART Interrupts
Thereꢀareꢀ2ꢀinterruptsꢀforꢀUART:ꢀreceiverꢀinterruptꢀ(URX),ꢀandꢀ
transmitterꢀinterruptꢀ(UTX).ꢀURXꢀhappensꢀwhenꢀreceiveꢁdataꢀisꢀ
readyꢀandꢀtheꢀreceiverꢀneedsꢀtoꢀbeꢀserviced.ꢀUTXꢀhappensꢀ
whenꢀcurrentꢀtransmissionꢀisꢀcompleted.ꢀErrorsꢀareꢀindicatedꢀbyꢀ
bitsꢀofꢀUARTꢀstatusꢀregisterꢀ(USTR).ꢀOtherꢀsequencesꢀofꢀUARTꢀ
interruptsꢀareꢀtheꢀsameꢀwithꢀthoseꢀdescriptionsꢀabove.
ꢀ
T1 Interrupt
TheꢀIRT1ꢀ(TIMER1ꢀinterruptꢀrequest)ꢀflagꢀwillꢀbeꢀsetꢀwhileꢀT1ꢀ
overflows.ꢀWithꢀIET1ꢀ(TIMER1ꢀinterruptꢀenable)ꢀbeingꢀset,ꢀtheꢀ
T1ꢀinterruptꢀwillꢀexecute,ꢀandꢀinterruptꢀmaskꢀflagꢀwillꢀbeꢀcleared.ꢀ
Hardwareꢀwillꢀpushꢀ‘PC’,ꢀ ꢀ ‘Pꢀ’ꢀRegisterꢀtoꢀstackꢀandꢀsetꢀ
Verꢀ2.5ꢀ
13
/75
ꢀ
9/16/2008ꢀ
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
