ST2202A
6. CPU
ꢀ
Register Model
ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
7ꢀ
0ꢀ
0ꢀ
0ꢀ
0ꢀ
0ꢀ
ꢀ
AccumulatorꢀAꢀ
A
Y
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
IndexꢀRegisterꢀYꢀ
ꢀ
IndexꢀRegisterꢀXꢀ
X
ꢀ
ProgramꢀCounterꢀPCꢀ
PCH
PCL
S
ꢀ
StackꢀPointerꢀSꢀ
1
ꢀ
directionꢀofꢀeitherꢀtheꢀprogramꢀorꢀinterruptsꢀ(IRQ).ꢀTheꢀstackꢀ
allowsꢀsimpleꢀimplementationꢀofꢀnestedꢀsubroutinesꢀandꢀ
multipleꢀlevelꢀinterrupts.ꢀTheꢀstackꢀpointerꢀisꢀinitializedꢀbyꢀtheꢀ
user’sꢀsoftware.ꢀ
ꢀ
ꢀ
Accumulator (A)
TheꢀAccumulatorꢀisꢀaꢀgeneralꢁpurposeꢀ8ꢁbitꢀregisterꢀthatꢀstoresꢀ
theꢀresultsꢀofꢀmostꢀarithmeticꢀandꢀlogicꢀoperations.ꢀInꢀaddition,ꢀ
theꢀaccumulatorꢀusuallyꢀcontainsꢀoneꢀofꢀtheꢀtwoꢀdataꢀwordsꢀ
usedꢀinꢀtheseꢀoperations.
ꢀ
ꢀ
ꢀ
Program Counter (PC)
Theꢀ16ꢁbitꢀProgramꢀCounterꢀregisterꢀprovidesꢀtheꢀaddress,ꢀ
whichꢀstepꢀtheꢀmicroprocessorꢀthroughꢀsequentialꢀprogramꢀ
instructions.ꢀEachꢀtimeꢀtheꢀmicroprocessorꢀfetchesꢀandꢀ
instructionꢀfromꢀprogramꢀmemory,ꢀtheꢀlowerꢀbyteꢀofꢀtheꢀ
programꢀcounterꢀ(PCL)ꢀisꢀplacedꢀonꢀtheꢀlowꢁorderꢀbitsꢀofꢀtheꢀ
addressꢀbusꢀandꢀtheꢀhigherꢀbyteꢀofꢀtheꢀprogramꢀcounterꢀ(PCH)ꢀ
isꢀplacedꢀonꢀtheꢀhighꢁorderꢀ8ꢀbits.ꢀTheꢀcounterꢀisꢀincrementꢀ
eachꢀtimeꢀanꢀinstructionꢀorꢀdataꢀisꢀfetchedꢀfromꢀprogramꢀ
memory.ꢀ
ꢀ
Index Registers (X,Y)
Thereꢀareꢀtwoꢀ8ꢁbitꢀIndexꢀRegistersꢀ(
X
ꢀandꢀY),ꢀwhichꢀmayꢀbeꢀ
usedꢀtoꢀcountꢀprogramꢀstepsꢀorꢀtoꢀprovideꢀandꢀindexꢀvalueꢀtoꢀ
beꢀusedꢀinꢀgeneratingꢀanꢀeffectiveꢀaddress.ꢀWhenꢀexecutingꢀanꢀ
instruction,ꢀwhichꢀspecifiesꢀindexedꢀaddressing,ꢀtheꢀCPUꢀ
fetchesꢀtheꢀOPꢀcodeꢀandꢀtheꢀbaseꢀaddress,ꢀandꢀmodifiesꢀtheꢀ
addressꢀbyꢀaddingꢀtheꢀindexꢀregisterꢀtoꢀitꢀpriorꢀtoꢀperformingꢀ
theꢀdesiredꢀoperation.ꢀPreꢀorꢀpostꢁindexingꢀofꢀindirectꢀ
addressesꢀisꢀpossible.ꢀ
ꢀ
ꢀ
ꢀ
Status Register (P)
ꢀ
Stack Pointer (S)
Theꢀ8ꢁbitꢀProcessorꢀStatusꢀRegisterꢀcontainsꢀsevenꢀstatusꢀflags.ꢀ
Someꢀofꢀtheseꢀflagsꢀareꢀcontrolledꢀbyꢀprogram;ꢀothersꢀmayꢀbeꢀ
alsoꢀcontrolledꢀbyꢀtheꢀCPUꢀasꢀwell.ꢀTheꢀinstructionꢀsetꢀcontainsꢀ
aꢀmemberꢀofꢀconditionalꢀbranchꢀinstructionsꢀthatꢀareꢀdesignedꢀ
toꢀallowꢀtestingꢀofꢀtheseꢀflags.ꢀReferꢀtoꢀTABLEꢀ6ꢁ1
TheꢀStackꢀPointerꢀisꢀanꢀ8ꢁbitꢀregister,ꢀwhichꢀisꢀusedꢀtoꢀcontrolꢀ
theꢀaddressingꢀofꢀtheꢀvariableꢁlengthꢀstack.ꢀIt’sꢀrangeꢀfromꢀ
100Hꢀtoꢀ1FFHꢀtotalꢀforꢀ256ꢀbytesꢀ(128ꢀlevelꢀdeep).ꢀTheꢀstackꢀ
pointerꢀisꢀautomaticallyꢀincrementꢀandꢀdecrementꢀunderꢀcontrolꢀ
ofꢀtheꢀmicroprocessorꢀtoꢀperformꢀstackꢀmanipulationsꢀunderꢀ
ꢀ
TABLE 6-1 Status Register (P)
Bit 4 Bit 3
Bꢀ Dꢀ
Bit 7
Nꢀ
Bit 6
Vꢀ
Bit 5
1ꢀ
Bit 2
Iꢀ
Bit 1
Zꢀ
Bit 0
Cꢀ
Bitꢀ7:ꢀ ꢀ ꢀ N :ꢀSignedꢀflagꢀbyꢀarithmeticꢀ
Bitꢀ3:ꢀ ꢀ ꢀ D :ꢀDecimalꢀmodeꢀflagꢀ
1ꢀ=ꢀNegativeꢀ
1ꢀ=ꢀDecimalꢀmodeꢀ
0ꢀ=ꢀPositiveꢀ
Bitꢀ6:ꢀ ꢀ ꢀ V :ꢀOverflowꢀofꢀsignedꢀArithmeticꢀflagꢀ
0ꢀ=ꢀBinaryꢀmodeꢀ
Bitꢀ2:ꢀ ꢀ ꢀ I :ꢀInterruptꢀdisableꢀflagꢀ
1ꢀ=ꢀNegativeꢀ
1ꢀ=ꢀInterruptꢀdisableꢀ
0ꢀ=ꢀPositiveꢀ
ꢀ
0ꢀ=ꢀInterruptꢀenableꢀ
Bitꢀ1:ꢀ ꢀ ꢀ Z :ꢀZeroꢀflagꢀ
1ꢀ=ꢀZeroꢀ
0ꢀ=ꢀNonꢀzero
ꢀ
Bitꢀ4:ꢀ ꢀ ꢀ B :ꢀBRKꢀinterruptꢀflagꢀ
Bitꢀ0:ꢀ ꢀ ꢀ C :ꢀCarryꢀflagꢀ
1ꢀ=ꢀBRKꢀinterruptꢀoccurꢀ
1ꢀ=ꢀCarryꢀ
0ꢀ=ꢀNonꢀBRKꢀinterruptꢀoccurꢀ
0ꢀ=ꢀNonꢀcarry
ꢀ
Verꢀ2.5ꢀ
7/75
ꢀ
9/16/2008ꢀ
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