U632H64
Write Cycle #1: W-controlledj
tcW
(12)
Ai
Address Valid
(17)
th(A)
tsu(E)
(21)
E
tsu(A-WH)
(16)
W
tw(W)
(13)
tsu(A)
(15)
tsu(D)
th(D)
(20)
(19)
Input Data Valid
ten(W)
High Impedance
DQi
Input
tdis(W)
(22)
(23)
DQi
Output
Previous Data Valid
Write Cycle #2: E-controlledj
tcW
Address Valid
tw(E)
(12)
Ai
E
tsu(A)
(15)
th(A)
(18)
(21)
tsu(W)
(14)
W
tsu(D) (19)
Input Data Valid
High Impedance
th(D)
(20)
DQi
Input
DQi
Output
undefined
L- to H-level
H- to L-level
i: If W is LOW and when E goes LOW, the outputs remain in the high impedance state.
j: E or W must be VIH during address transition.
Rev 1.1
August 15, 2006
STK Control #ML0047
6
SIMTEK [ SIMTEK CORPORATION ]
