SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Programming Sequences
The programming sequence for the SiI3114 is about the same as for the SiI3112 or SiI3512. However, SiI3114
supports up to four SATA devices (instead of two for the others).
In order to minimize the legacy BIOS code changes, the SiI3114 uses “Master/Slave” type of emulation for the
register mapping of Base Address Register 0 ~ 4 (between SATA device 0 and device 2 or SATA device 1 and
device 3). Therefore, the programmer will not be able to access SATA device 0 and device 2 (or device 1 and
device 3) at the same time when BAR 0~4 are used to access the devices. SATA device 0 is equivalent to legacy
Primary Master device, SATA device 1 is equivalent to legacy Secondary Master device, SATA device 2 is
equivalent to legacy Primary Slave device, and SATA device 3 is equivalent to legacy Secondary Slave device.
In order to access all four SATA devices simultaneously, BAR5 registers must be used. They have a similar
structure to the previous 2 channel controllers for the first 512 bytes (for device 0 and device 1), but they have an
additional 512 bytes of registers to duplicate the register structures for the additional two SATA channels (device 2
and device 3).
When BAR5 registers are used to access all four SATA devices simultaneously, the interrupt steering bit at bit 1 in
BAR5 offset 200h must be set. The interrupt steering bit must be reset when “Master/Slave” type of emulation is
used. The reset value for this bit is 0. This bit must be remained set for simultaneous 4 channels operation. Any
write operation to the BAR5 offset 200h register should mask the "Interrupt steering" bit and not to reset it by
accident.
Recommended Initialization Sequence for the SiI3114
The recommended initialization sequence for the SiI3114 is detailed below.
Initialize PCI Configuration Space registers:
• Initialize Base Address Register 0 with the address of an 8-byte range in I/O space.
• Initialize Base Address Register 1 with the address of a 4-byte range in I/O space.
• Initialize Base Address Register 2 with the address of an 8-byte range in I/O space.
• Initialize Base Address Register 3 with the address of a 4-byte range in I/O space.
• Initialize Base Address Register 4 with the address of a 16-byte range in I/O space.
• Initialize Base Address Register 5 with the address of a 1024-byte range in memory space.
• To enable the bios expansion ROM, initialize the Expansion ROM Base Address Register with the address
of a 512KB range in memory space.
• Enable I/O space access, memory space access, and bus master operation by setting bits [2:0] of the PCI
Command register.
Note: The preceding configuration space register initialization is normally done by the motherboard BIOS in PC
type systems.
If the arbiter’s default FIFO read/write request thresholds are not suitable for the application they may be changed
via the FIFO Valid Byte Count and Control Channel x register. The read threshold is defined by bits [05:00], and
the write threshold is defined by bits [13:08] in the FIFO Valid Byte Count and Control – Channel x register. In
most environments, setting these bit fields to zero results in the best utilization of the PCI bus by the SiI3114
controller.
If interrupt driven operation is not desired, set bits [23:22] of the System Configuration Status and Command
register to block interrupts from reaching the PCI bus.
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
SILICONIMAGE [ Silicon image ]
