SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Serial ATA SActive
Address Offset: 10CH / 18CH / 30CH / 38CH
Access Type: Read/Write 1/Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
SActive bits
The bits of this register may be written with a 1, but are cleared if the corresponding bits of the second dword of a
FIS are set when the SDevice Bits FIS is received. All 32 bits may be cleared by writing 0x0000_0000 to the
register; individual bits may not be cleared except by the hardware.
SMisc
Address Offset: 140H / 1C0H / 340H / 3C0H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
This register contains bits for controlling Serial ATA power management, ComWake, loopback modes, and FIS
transfers.
• Bit [31]: FIS_Done (R/W) – This bit is used to indicate to the link logic that all the data for the Transparent
FIS has been transferred and that the link can proceed to close out the FIS. This is used in Transparent
FIS transmission. Please refer to the “FIS Support” section on page 85 for more details.
• Bit [30]: Transmit_FIS (W)– This bit is used to signal the link logic to start the process of transmitting a
Transparent FIS. Please refer to the “FIS Support” section on page 85 for more details.
• Bit [29]: Transmit_OK (R)– This bit is used in Transparent FIS transmission. It is used by the link to signal
to the host that the current Transparent FIS has been successfully transferred to the device, and that R_OK
has been received.
• Bit [28]: IFIS_OK (R)– This bit is used in the reception of Interlocked FISes. This bit is set by the link logic
to inform the host that the current Interlocked FIS has been successfully received with no errors.
• Bit [27]: IntrlckFIS (R)– This bit is set to indicate to the host driver that the link has detected an the arrival
of an interlocked FIS and that the host should set up the DMA engine to start transfer of data
• Bit [26]: Reject_IFIS (W)– This bit is set by the host driver to indicate to the link that the current Interlocked
FIS should be rejected. The link logic will respond to the device with an R_ERR when the complete FIS has
been received.
• Bit [25]: Accept_IFIS (W)– This bit is set by the host driver to indicate to the link that the current interlocked
FIS should be accepted. The link logic will respond to the device with R_OK
• Bit [24]: Rx_IFIS (W)– This bit is set by the host driver to inform the link/transport logic that the host has
set up the DMA engine to transfer the incoming Interlocked FIS and that the DMA cycles can begin
• Bit [23]: SDB (R) – This bit indicates that a Set Device Bits FIS has been received
• Bit [22]: pterr (R) – This bit indicates that a Protocol Error has occurred. An interrupt will be generated if bit
20 of SIEN is set.
• Bit [21]: Scr_dis (R/W)– This bit disables the scrambling of data on the serial ATA bus. This is used only for
debugging purposes and should not be changed by the user
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
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