SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Write Operation
Wait until bit 27(DRQ) in the Channel x Task File Register 1 register is set.
Continue to write data via the Channel x Task File Register 0 register until the expected number of
sectors of data per interrupt are written.
Wait for a channel interrupt.
If controller interrupts are disabled, poll for the interrupt by reading the Channel x Task File Timing
+ Configuration + Status register. If bit 12 is set, a watchdog timeout has occurred. If bit 11 is set,
the ATA device is interrupting.
If the watchdog timeout bit is set,
Write 1 to bit 12 in the Channel x Task File Timing + Configuration + Status register to clear
watchdog timeout status.
The watchdog timeout represents a fatal error as far as the current ATA command is concerned.
A course of action that might be appropriate at this point might be to reset and reinitialize the ATA
channel and then retrying the command that failed.
If the ATA device interrupt bit is set,
Read the device status at bits [31:24] in the Channel x Task File Register 1 register to clear the
device interrupt and determine if there was an error.
Write 1 to bit 18 of the PCI Bus Master – Channel x Register to clear the ATA interrupt.
If no error, repeat the write operation steps until all data for the write command has been
transferred or an error has been detected.
PIO Mode Read Ahead Operation
Read ahead operation allows the controller to “pre-fetch” data and store it in the controller’s channel FIFO, where
it will later be retrieved by the host. This mode of operation has the potential to speed-up PIO data transfers by
not forcing the host to wait the programmed PIO cycle time for every access to the task file data register. The
amount of any speed increase will depend on the PIO mode in use, the characteristics of the host PCI bus, as
well as the speed of the host processor.
To use the controller’s PIO read ahead capability, make the following changes to the “Read Operation” portion of
the “PIO Mode Read/Write Operation” and “Watchdog Timer Operation” sections:
• Just prior to retrieving the read data, set the read ahead byte count by programming bits [15:00] in the
Channel x Virtual DMA/PIO Read Ahead Byte Count register with the exact number of bytes to be read for
the interrupt.
• Instead of reading the Channel x Task File Register 0 register to retrieve the data, read the Channel x Read
Ahead Data register.
MDMA/UDMA Read/Write Operation
Once the SiI3114 is initialized via the initialization sequence described in the “Recommended Initialization
Sequence for the SiI3114” section, and the SATA device has been initialized for MDMA/UDMA mode data transfer
per the guidelines in the “Serial ATA Device Initialization” section, DMA read/write operations may be performed
by following the programming sequence described below.
Issue a DMA read/write command to the device following the steps in the “Issue ATA Command” section on page
76.
Program Bus Master Registers
Clear bit 17 in the PCI Bus Master – Channel x register. This bit is set if an error occurred during the
previous DMA access.
Clear bit 18 in the PCI Bus Master – Channel x register. This bit is set if an interrupt occurred during the
previous DMA access.
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
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