SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
• Bit [22]: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect.
The device is always capable of DMA as a PCI bus master.
• Bit [21]: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect.
The device is always capable of DMA as a PCI bus master.
• Bit [20]: Watchdog (R): This bit is a copy of bit 12 in Channel X Task File Configuration + Status register.
• Bit [19]: Channel X Buffer empty (R). This bit set indicates the Channel X FIFO is empty.
• Bit [18]: Channel X DMA Comp (R/W1C) – Channel X DMA Completion Interrupt. During write DMA
operation, this bit set indicates that the Channel X interrupt has been asserted and all data has been
written to system memory. During Read DMA, this bit set indicates that the Channel X interrupt has been
asserted.
This bit must be cleared by software (Write 1 to Clear) when set during DMA operation (PBM Enable, bit 0
is set).
• Bit [17]: PBM Error (R/W1C) – PCI Bus Master Error – Channel 0. This bit set indicates that a PCI bus
error occurred while the SiI3114 was bus master. Additional information is available in the PCI Status
register in PCI Configuration space.
• Bit [16]: PBM Active (R) – PCI Bus Master Active – Channel 0. This bit set indicates that the SiI3114 is
currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data
transfers have completed or PBM Enable bit is not set.
• Bit[15] : Watchdog Timer Status ( R ) – This bit is an ORed result of bit 12 in the four Channel Task File
Timing + Configuration + Status registers. When set indicates that one or more of the four Channel
Watchdog timers has expired.
• Bit[14] : Channel X+1 DMA Completion Interrupt Status ( R ) – This bit is a copy of the Channel X DMA
Completion Interrupt (bit 18) in the PCI Bus Master register for Channel X+1.
• Bit [13:08]: Software Data (R/W) – System Software Data Storage. This bit field is used for read/write data
storage by the system. The properties of this bit field are detailed below.
Table 24. Software Data Byte, Base Address 5, Offset 10H
Bit Location
[13:12]
Default
XXB
Description
Not cleared by any reset
Cleared by PCI reset
[11:10]
00B
[09:08]
XXB
Cleared only by a D0-D3 power state change
• Bit [07]: Reserved (R). This bit is reserved and returns zeros on a read.
• Bit [06]: SATAINTX+1 – This bit is the logical OR of all Serial ATA interrupt sources for channel X+1.
• Bit [05]: Reserved (R). This bit is reserved and returns zeros on a read.
• Bit [04]: SATAINTX – This bit is the logical OR of all Serial ATA interrupt sources for channel X.
• Bit [03]: PBM Rd-Wr (R/W) – PCI Bus Master Read-Write Control. This bit is set to specify a DMA write
operation from Channel X to system memory. This bit is cleared to specify a DMA read operation from
system memory to the Channel X device.
• Bit [02:01]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [00]: PBM Enable (R/W) – PCI Bus Master Enable – Channel X. This bit is set to enable PCI bus
master operations for Channel X. PCI bus master operations can be halted by clearing this bit, but will
erase all state information in the control logic. If this bit is cleared while the PCI bus master is active, the
operation will be aborted and the data discarded. While this bit is set, accessing Channel X Task File or
PIO data registers will be terminated with Target-Abort.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
