SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
FIFO Valid Byte Count and Control – Channel X
Address Offset: 40H / 44H / 240H / 244H
Access Type: Read/Write
Reset Value: 0x0000_0000
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FIFO Wr
Req Ctrl
FIFO Rd
Req Ctrl
Reserved
FIFO Valid Byte Count
Reserved
Reserved
This register defines the FIFO valid byte count register and PCI bus request control for Channel X in the SiI3114.
The register bits are defined below.
The FIFO Write Request Control and FIFO Read Request Control fields in these registers provide threshold
settings for establishing when PCI requests are made to the Arbiter. The Arbiter arbitrates among the four
requests using fixed priority with masking. The fixed priority is, from highest to lowest: channel 0; channel 1;
channel 2; and channel 3. If multiple requests are present, the arbiter grants PCI bus access to the highest
priority channel that is not masked. That channel’s request is then masked as long as any unmasked requests are
present.
• Bit [31:25]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [24:16]: FIFO Valid Byte Count (R). This bit field provides the valid byte count for the data FIFO for
Channel X. A value of 000H indicates empty, while a value of 100H indicates a full FIFO with 256 bytes.
• Bit [15:11]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [10:08]: FIFO Wr Req Ctrl (R/W) – FIFO Write Request Control. This bit field defines the FIFO
threshold to assign priority when requesting a PCI bus write operation. A value of 00H indicates that write
request priority is set whenever the FIFO contains greater than 32 bytes, while a value of 07H indicates that
write request priority is set whenever the FIFO contains greater than 7x32 bytes (=224 bytes). This bit field
is useful when multiple DMA channels are competing for the PCI bus.
• Bit [07:03]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [02:00]: FIFO Rd Req Ctrl (R/W) – FIFO Read Request Control. This bit field defines the FIFO
threshold to assign priority when requesting a PCI bus read operation. A value of 00H indicates that read
request priority is set whenever the FIFO has greater than 32 bytes available space, while a value of 07H
indicates that read request priority is set whenever the FIFO has greater than 7x32 bytes (=224 bytes)
available space. This bit field is useful when multiple DMA channels are competing for accessing the PCI
bus.
System Configuration Status – Command
Address Offset: 48H
Access Type: Read/Write
Reset Value: 0x0000_0000
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Reserved
Reserved
Reserved
This register defines the system configuration status and command register for the SiI3114. The register bits are
defined below.
• Bit [31:26]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [25]: Chnl3 Int Block (R/W) – Channel3 Interrupt Block. This bit is set to block interrupts from Channel
3.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
