SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
• Bit [31:28]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [27]: Memory Init Done (R) – This bit set indicates that the memory initialization sequence is done. The
memory sequence is activated upon the release of reset.
• Bit [26]: Mem Init (R) – Memory Initialized. This bit set indicates that the memory was initialized properly (a
correct data sequence was read from the Flash.)
• Bit [25]: Mem Access Start (R/W) – Memory Access Start. This bit is set to initiate an operation to Flash
memory. This bit is cleared when the operation is complete.
• Bit [24]: Mem Access Type (R/W) – Memory Access Type. This bit is set to define a read operation from
Flash memory. This bit is cleared to define a write operation to Flash memory.
• Bit [23:19]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [18:00]: Memory Address (R/W). This bit field is programmed with the address for a flash memory read
or write access.
Flash Memory Data
Address Offset: 54H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
GPIO Control
Memory Data
This register defines the data register for the Flash memory and GPIO interface in the SiI3114. The system writes
to this register for a write operation to Flash memory, and reads from this register on a read operation from Flash
memory. The GPIO Control bits control operation of the Flash data lines for use as General Purpose I/O. GPIO is
only enabled when the GPIOEN pin is pulled high.
• Bit [31:16]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [15:08]: GPIO Control – The bits of this field are written to control the output type for corresponding
Flash data lines; if a bit is a 1 the corresponding output is an open drain output (only driven low); if a 0 the
corresponding output is always driven. The bits of this field, when read, report signal transition detection on
the corresponding Flash data input; reading the register resets the transition detect bits.
• Bit [07:00]: Memory Data (R/W) – Flash Memory Data. This bit field is used for Flash write data on a write
operation, and returns the Flash read data on a read operation.
This register defines the data register for the Flash memory and GPIO interface in the Taurus. The GPIO Control
bits control operation of the Flash data lines for use as General Purpose I/O. GPIO is enabled when the GPIOEN
pin is pulled high.
EEPROM Memory Address – Command + Status
Address Offset: 58H
Access Type: Read/Write
Reset Value: 0x0800_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Reserved
Mem Address
This register defines the address and command/status register for EEPROM memory interface in the SiI3114.
The register bits are defined below.
• Bit [31:29]: Reserved (R). This bit field is reserved and returns zeros on a read.
© 2007 Silicon Image, Inc.
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SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
