SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
PCI Bus Master – Channel X
Address Offset: 00H / 08H / 200H / 208H
Access Type: Read/Write
Reset Value: 0x0000_XX00
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Software
Reserved
This register defines the PCI bus master register for Channel X in the SiI3114. The register bits are defined below.
• Bit [31:24]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [23]: PBM Simplex (R) – PCI Bus Master Simplex Only. This read-only bit field is hardwired to zero to
indicate that all channels can operate as PCI bus master at any time.
• Bit [22]: PBM DMA Cap 1 (R/W) – PCI Bus Master DMA Capable – Device 1. This bit field has no effect.
The device is always capable of DMA as a PCI bus master.
• Bit [21]: PBM DMA Cap 0 (R/W) – PCI Bus Master DMA Capable – Device 0. This bit field has no effect.
The device is always capable of DMA as a PCI bus master.
• Bit [20:19]: Reserved (R). This bit field is reserved and returns zeros on a read.
• Bit [18]: Channel X DMA Comp (R/W1C) – Channel X DMA Completion Interrupt. During write DMA
operation, this bit set indicates that the Channel X interrupt has been asserted and all data has been
written to system memory. During Read DMA, This bit set indicates that the Channel X interrupt has been
asserted.
This bit must be cleared (Write 1 to Clear) by software when set during DMA operation (PBM Enable, bit 0
is set).
• Bit [17]: PBM Error (R/W1C) – PCI Bus Master Error – Channel X. This bit set indicates that a PCI bus
error occurred while the SiI3114 was bus master. Additional information is available in the PCI Status
register in PCI Configuration space.
• Bit [16]: PBM Active (R) – PCI Bus Master Active – Channel X. This bit set indicates that the SiI3114 is
currently active in a data transfer as PCI bus master. This bit is cleared by the hardware when all data
transfers have completed or PBM Enable bit is not set.
• Bit[15]: Watchdog Timer Status (R) – This bit is an ORed result of bit 12 in the four Channel Task File
Timing + Configuration + Status registers. When set indicates that one or more of the four Channel
Watchdog timers has expired. This bit appears only in the Channel 0 (offset 00H) and Channel 2 (offset
200H) registers; this bit is reserved in the Channel 1 (offset 08H) and Channel 3 (offset 208H) registers.
• Bit[14] : Channel X+1 Interrupt Status (R) – This bit is a copy of the Channel X DMA Completion Interrupt
(bit 18) in the PCI Bus Master (this) register for Channel X+1. This bit appears only in the Channel 0 (offset
00H) and Channel 2 (offset 200H) registers; this bit is reserved in the Channel 1 (offset 08H) and Channel 3
(offset 208H) registers.
• Bit [13:08]: Software Data (R/W) – System Software Data Storage. This bit field is used for read/write data
storage by the system. The properties of this bit field are detailed below. This bit field appears only in the
Channel 0 (offset 00H) and Channel 2 (offset 200H) registers; this bit field is reserved in the Channel 1
(offset 08H) and Channel 3 (offset 208H) registers.
Table 23. Software Data Byte, Base Address 5, Offset 00H
Bit Location
[13:12]
Default
XXB
Description
Not cleared by any reset
Cleared by PCI reset
[11:10]
00B
[09:08]
XXB
Cleared only by a D0-D3 power state change
• Bit [07:04]: Reserved (R). This bit field is reserved and returns zeros on a read.
© 2007 Silicon Image, Inc.
53
SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
