SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Summary Interrupt Status
Address Offset: 214H
Access Type: Read/Write
Reset Value: 0x0808_0808
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
This register provides a single register containing a summary of the interrupt status of all four channels.
The Interrupt Status bits are replicas of bit 11 of the Task File Configuration + Status register. The other bits are
replicas of bits in the PCI Bus Master2 registers.
PRD Address – Channel X
Address Offset: 20H / 28H / 220H / 228H
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PRD Address
This register reflects the current DMA address and uses for diagnostic purposes only.
• Bit [31:00]: PRD Address (R) – This field is the current DMAAddress.
PCI Bus Master Byte Count – Channel X
Address Offset: 24H / 2CH / 224H / 22CH
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Byte Count High
Byte Count Low
This register defines the byte count register in the PCI bus master logic for Channel X in the SiI3114. The register
bits are defined below.
• Bit [31]: End of Table (R). This bit set indicates that this is the last entry in the PRD table.
• Bit [30:16] Byte Count High (R). This bit field is the PRD entry byte count extension for Large Block
Transfer Mode. Under generic mode, this bit field is reserved and returns zeros on a read.
• Bit [15:00] Byte Count Low (R). This bit field reflects the current DMA byte count value.
SiI-DS-0103-D
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© 2007 Silicon Image, Inc.
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